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Commit 022be25c authored by Punnaiah Choudary Kalluri's avatar Punnaiah Choudary Kalluri Committed by David S. Miller
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net: macb: Add support for sgmii phy interface 



This patch adds support for the sgmii phy interface.

Signed-off-by: default avatarPunnaiah Choudary Kalluri <punnaia@xilinx.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 0208e951

drivers/net/ethernet/cadence/macb.c

+4 −0
Original line number Diff line number Diff line
@@ -1682,6 +1682,8 @@ static void macb_init_hw(struct macb *bp) 
	macb_set_hwaddr(bp);



	config = macb_mdc_clk_div(bp);

	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)

		config |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);

	config |= MACB_BF(RBOF, NET_IP_ALIGN);	/* Make eth data aligned */

	config |= MACB_BIT(PAE);		/* PAuse Enable */

	config |= MACB_BIT(DRFCS);		/* Discard Rx FCS */
@@ -2416,6 +2418,8 @@ static int macb_init(struct platform_device *pdev) 
	/* Set MII management clock divider */

	val = macb_mdc_clk_div(bp);

	val |= macb_dbw(bp);

	if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)

		val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);

	macb_writel(bp, NCFGR, val);



	return 0;

drivers/net/ethernet/cadence/macb.h

+5 −0
Original line number Diff line number Diff line
@@ -215,12 +215,17 @@ 
/* GEM specific NCFGR bitfields. */

#define GEM_GBE_OFFSET		10 /* Gigabit mode enable */

#define GEM_GBE_SIZE		1

#define GEM_PCSSEL_OFFSET	11

#define GEM_PCSSEL_SIZE		1

#define GEM_CLK_OFFSET		18 /* MDC clock division */

#define GEM_CLK_SIZE		3

#define GEM_DBW_OFFSET		21 /* Data bus width */

#define GEM_DBW_SIZE		2

#define GEM_RXCOEN_OFFSET	24

#define GEM_RXCOEN_SIZE		1

#define GEM_SGMIIEN_OFFSET	27

#define GEM_SGMIIEN_SIZE	1





/* Constants for data bus width. */

#define GEM_DBW32		0 /* 32 bit AMBA AHB data bus width */