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Commit 0181a16f authored by Karthik Anantha Ram's avatar Karthik Anantha Ram
Browse files

msm: camera: isp: Disable clk gating in IFE top 



Disable auto clk gating for all core clocks, ahb & NOC.

CRs-Fixed: 2705869
Change-Id: I74ad58e1c8308edcd19ac6414a25a0f7fafce3cd
Signed-off-by: default avatarKarthik Anantha Ram <kartanan@codeaurora.org>
parent 1b7fd539

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver3.c

+6 −9
Original line number Diff line number Diff line
@@ -366,23 +366,20 @@ int cam_vfe_top_ver3_init_hw(void *device_priv, 


	top_priv->hw_clk_rate = 0;



	/**

	 * Auto clock gating is enabled by default, but no harm

	 * in setting the value we expect.

	 */

	CAM_DBG(CAM_ISP, "Enabling clock gating at IFE top");

	/* Disable clock gating at IFE top */

	CAM_DBG(CAM_ISP, "Disable clock gating at IFE top");



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->core_cgc_ovd_0, 0x0);

		common_data.common_reg->core_cgc_ovd_0, 0xFFFFFFFF);



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->core_cgc_ovd_1, 0x0);

		common_data.common_reg->core_cgc_ovd_1, 0xFF);



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->ahb_cgc_ovd, 0x0);

		common_data.common_reg->ahb_cgc_ovd, 0x1);



	cam_soc_util_w_mb(common_data.soc_info, VFE_CORE_BASE_IDX,

		common_data.common_reg->noc_cgc_ovd, 0x0);

		common_data.common_reg->noc_cgc_ovd, 0x1);



	top_priv->top_common.hw_version =

		cam_io_r_mb(common_data.soc_info->reg_map[0].mem_base +