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Commit 0126abd4 authored by Aaron Liu's avatar Aaron Liu Committed by Alex Deucher
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drm/amdgpu: fix no interrupt issue for renoir emu 



In renoir's ih model, there's a change in mmIH_CHICKEN
register, that limits IH to use physical address directly.
Those chicken bits need to be programmed first.

Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarAaron Liu <aaron.liu@amd.com>
Reviewed-by: default avatarHuang Rui <ray.huang@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 61bdb39c

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+1 −1
Original line number Diff line number Diff line
@@ -247,7 +247,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
		WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl);

	}



	if (adev->asic_type == CHIP_ARCTURUS &&

	if ((adev->asic_type == CHIP_ARCTURUS || adev->asic_type == CHIP_RENOIR) &&

		adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {

		if (adev->irq.ih.use_bus_addr) {

			ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN);