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Commit 00e930d8 authored by Ludovic Barre's avatar Ludovic Barre Committed by Ulf Hansson
Browse files

mmc: mmci: add clock divider for stm32 sdmmc 



The STM32 sdmmc variant has a different clock divider.

Signed-off-by: default avatarLudovic Barre <ludovic.barre@st.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 15878e58

drivers/mmc/host/mmci.c

+2 −0
Original line number Diff line number Diff line
@@ -1862,6 +1862,8 @@ static int mmci_probe(struct amba_device *dev, 
	 */

	if (variant->st_clkdiv)

		mmc->f_min = DIV_ROUND_UP(host->mclk, 257);

	else if (variant->stm32_clkdiv)

		mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);

	else if (variant->explicit_mclk_control)

		mmc->f_min = clk_round_rate(host->clk, 100000);

	else

drivers/mmc/host/mmci.h

+2 −0
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ struct mmci_host; 
 * @data_cmd_enable: enable value for data commands.

 * @st_sdio: enable ST specific SDIO logic

 * @st_clkdiv: true if using a ST-specific clock divider algorithm

 * @stm32_clkdiv: true if using a STM32-specific clock divider algorithm

 * @datactrl_mask_ddrmode: ddr mode mask in datactrl register.

 * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register

 * @blksz_datactrl4: true if Block size is at b4..b16 position in datactrl
@@ -269,6 +270,7 @@ struct variant_data { 
	u8			datacnt_useless:1;

	u8			st_sdio:1;

	u8			st_clkdiv:1;

	u8			stm32_clkdiv:1;

	u8			blksz_datactrl16:1;

	u8			blksz_datactrl4:1;

	u32			pwrreg_powerup;