Commit 00c674e4 authored Nov 18, 2013 by Thierry Reding Committed by Peter De Schrijver Nov 26, 2013

clk: tegra: Fix clock rate computation

The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.

This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.

Signed-off-by: Thierry Reding <treding@nvidia.com>

parent 480fe6f4

drivers/clk/tegra/clk-pll.c

+2 −0

Original line number	Original line	Diff line number	Diff line
	@@ -411,6 +411,8 @@ static int _calc_rate(struct clk_hw hw, struct tegra_clk_pll_freq_table cfg,
	return -EINVAL;		return -EINVAL;
	}		}

			cfg->output_rate >>= p_div;

	if (pll->params->pdiv_tohw) {		if (pll->params->pdiv_tohw) {
	ret = _p_div_to_hw(hw, 1 << p_div);		ret = _p_div_to_hw(hw, 1 << p_div);
	if (ret < 0)		if (ret < 0)