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Commit 00ac6f6b authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu: add tiling flags for GFX9 (v2) 



v2: Marek: allow shifts >32 in AMDGPU_TILING_SET/GET

Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a8f1f1ce

include/uapi/drm/amdgpu_drm.h

+8 −2
Original line number Original line Diff line number Diff line
@@ -209,6 +209,7 @@ struct drm_amdgpu_gem_userptr { 
	__u32		handle;

	__u32		handle;

};

};





/* SI-CI-VI: */

/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */

/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */

#define AMDGPU_TILING_ARRAY_MODE_SHIFT			0

#define AMDGPU_TILING_ARRAY_MODE_SHIFT			0

#define AMDGPU_TILING_ARRAY_MODE_MASK			0xf

#define AMDGPU_TILING_ARRAY_MODE_MASK			0xf
@@ -227,10 +228,15 @@ struct drm_amdgpu_gem_userptr { 
#define AMDGPU_TILING_NUM_BANKS_SHIFT			21

#define AMDGPU_TILING_NUM_BANKS_SHIFT			21

#define AMDGPU_TILING_NUM_BANKS_MASK			0x3

#define AMDGPU_TILING_NUM_BANKS_MASK			0x3





/* GFX9 and later: */

#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT		0

#define AMDGPU_TILING_SWIZZLE_MODE_MASK			0x1f



/* Set/Get helpers for tiling flags. */

#define AMDGPU_TILING_SET(field, value) \

#define AMDGPU_TILING_SET(field, value) \

	(((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)

	(((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)

#define AMDGPU_TILING_GET(value, field) \

#define AMDGPU_TILING_GET(value, field) \

	(((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)

	(((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)





#define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1

#define AMDGPU_GEM_METADATA_OP_SET_METADATA                  1

#define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2

#define AMDGPU_GEM_METADATA_OP_GET_METADATA                  2