Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 009edd9a authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
Browse files

perf vendor events intel: Update IvyTown events to v20 



Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent e313477f

tools/perf/pmu-events/arch/x86/ivytown/pipeline.json

+0 −4
Original line number Original line Diff line number Diff line 
[

[

    {

    {

        "EventCode": "0x00",

        "Counter": "Fixed counter 0",

        "Counter": "Fixed counter 0",

        "UMask": "0x1",

        "UMask": "0x1",

        "EventName": "INST_RETIRED.ANY",

        "EventName": "INST_RETIRED.ANY",
@@ -9,7 +8,6 @@ 
        "CounterHTOff": "Fixed counter 0"

        "CounterHTOff": "Fixed counter 0"

    },

    },

    {

    {

        "EventCode": "0x00",

        "Counter": "Fixed counter 1",

        "Counter": "Fixed counter 1",

        "UMask": "0x2",

        "UMask": "0x2",

        "EventName": "CPU_CLK_UNHALTED.THREAD",

        "EventName": "CPU_CLK_UNHALTED.THREAD",
@@ -19,7 +17,6 @@ 
    },

    },

    {

    {

        "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",

        "PublicDescription": "Core cycles when at least one thread on the physical core is not in halt state.",

        "EventCode": "0x00",

        "Counter": "Fixed counter 1",

        "Counter": "Fixed counter 1",

        "UMask": "0x2",

        "UMask": "0x2",

        "AnyThread": "1",

        "AnyThread": "1",
@@ -29,7 +26,6 @@ 
        "CounterHTOff": "Fixed counter 1"

        "CounterHTOff": "Fixed counter 1"

    },

    },

    {

    {

        "EventCode": "0x00",

        "Counter": "Fixed counter 2",

        "Counter": "Fixed counter 2",

        "UMask": "0x3",

        "UMask": "0x3",

        "EventName": "CPU_CLK_UNHALTED.REF_TSC",

        "EventName": "CPU_CLK_UNHALTED.REF_TSC",