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Commit 009d9ed6 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
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drm/amdgpu: Change AI gfx/sdma/smu init sequence 



initialize gfx/sdma before dpm features enabled.

Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 3089aa22

drivers/gpu/drm/amd/amdgpu/soc15.c

+4 −4
Original line number Diff line number Diff line
@@ -529,6 +529,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) 
			amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block);

		else

			amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		if (!amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))
@@ -539,8 +541,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) 
#else

#	warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) {

			amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block);

			amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block);
@@ -551,6 +551,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) 
		amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);

		amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block);

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);

		if (adev->enable_virtual_display || amdgpu_sriov_vf(adev))

			amdgpu_device_ip_block_add(adev, &dce_virtual_ip_block);
@@ -560,8 +562,6 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) 
#else

#	warning "Enable CONFIG_DRM_AMD_DC for display support on SOC15."

#endif

		amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);

		amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);

		amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block);

		break;

	default: