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Commit 0070266e authored by Vipin Deep Kaur's avatar Vipin Deep Kaur
Browse files

spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout 



Propagate a change from 4.19 to 5.4 for SPI. 'commit 556e7c13ceaa
("spi: spi-msm-geni: Clear the RX fifo if FIFO has data after timeout")'.

Change-Id: Ica785f7b3cd3a9f9df6d173413ce136c2a018312
Signed-off-by: default avatarVipin Deep Kaur <vkaur@codeaurora.org>
parent 58329ca1

drivers/spi/spi-msm-geni.c

+12 −0
Original line number Diff line number Diff line
@@ -1384,9 +1384,21 @@ static void handle_fifo_timeout(struct spi_geni_master *mas, 
					struct spi_transfer *xfer)

{

	unsigned long timeout;

	u32 rx_fifo_status;

	int rx_wc, i;



	geni_se_dump_dbg_regs(&mas->spi_rsc, mas->base, mas->ipc);

	reinit_completion(&mas->xfer_done);



	/* Dummy read the rx fifo for any spurious data*/

	if (xfer->rx_buf) {

		rx_fifo_status = geni_read_reg(mas->base,

					SE_GENI_RX_FIFO_STATUS);

		rx_wc = (rx_fifo_status & RX_FIFO_WC_MSK);

		for (i = 0; i < rx_wc; i++)

			geni_read_reg(mas->base, SE_GENI_RX_FIFOn);

	}



	geni_cancel_m_cmd(mas->base);

	if (mas->cur_xfer_mode == FIFO_MODE)

		geni_write_reg(0, mas->base, SE_GENI_TX_WATERMARK_REG);