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Commit ffc3eb6f authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'sunxi-clk-for-4.15' of... 

Merge tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next

Pull Allwinner clock driver updates from Maxime Ripard:

  - Addition of sigma/delta modulation for the audio PLLs on the newer SoCs
  - A83t Display clocks supports
  - minor fixes that didn't have any impact on current features

* tag 'sunxi-clk-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: sun4i: Export video PLLs
  clk: sunxi-ng: Add A83T display clocks
  clk: sunxi-ng: sun8i: a23: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun6i: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun5i: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun4i: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: sun8i: h3: Use sigma-delta modulation for audio PLL
  clk: sunxi-ng: nm: Add support for sigma-delta modulation
  clk: sunxi-ng: Add sigma-delta modulation support
  clk: sunxi-ng: nm: Check if requested rate is supported by fractional clock
  clk: sunxi-ng: sun5i: Fix bit offset of audio PLL post-divider
  clk: sunxi-ng: a83t: Fix invalid csi-mclk mux offset
  clk: sunxi-ng: sun6i: Rename HDMI DDC clock to avoid name collision
  clk: sunxi-ng: sun6i: Export video PLLs
  clk: sunxi-ng: Implement reset control status readback
  clk: sunxi-ng: Fix missing CLK_SET_RATE_PARENT in ccu-sun4i-a10.c
  clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock
  clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
parents ae74ac08 4328a218

drivers/clk/sunxi-ng/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_gate.o 
lib-$(CONFIG_SUNXI_CCU)		+= ccu_mux.o

lib-$(CONFIG_SUNXI_CCU)		+= ccu_mult.o

lib-$(CONFIG_SUNXI_CCU)		+= ccu_phase.o

lib-$(CONFIG_SUNXI_CCU)		+= ccu_sdm.o



# Multi-factor clocks

lib-$(CONFIG_SUNXI_CCU)		+= ccu_nk.o

drivers/clk/sunxi-ng/ccu-sun4i-a10.c

+21 −7
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ 
#include "ccu_nkmp.h"

#include "ccu_nm.h"

#include "ccu_phase.h"

#include "ccu_sdm.h"



#include "ccu-sun4i-a10.h"
@@ -51,16 +52,29 @@ static struct ccu_nkmp pll_core_clk = { 
 * the base (2x, 4x and 8x), and one variable divider (the one true

 * pll audio).

 *

 * We don't have any need for the variable divider for now, so we just

 * hardcode it to match with the clock names.

 * With sigma-delta modulation for fractional-N on the audio PLL,

 * we have to use specific dividers. This means the variable divider

 * can no longer be used, as the audio codec requests the exact clock

 * rates we support through this mechanism. So we now hard code the

 * variable divider to 1. This means the clock rates will no longer

 * match the clock names.

 */

#define SUN4I_PLL_AUDIO_REG	0x008



static struct ccu_sdm_setting pll_audio_sdm_table[] = {

	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },

	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },

};



static struct ccu_nm pll_audio_base_clk = {

	.enable		= BIT(31),

	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),

	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),

	.sdm		= _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,

					 0x00c, BIT(31)),

	.common		= {

		.reg		= 0x008,

		.features	= CCU_FEATURE_SIGMA_DELTA_MOD,

		.hw.init	= CLK_HW_INIT("pll-audio-base",

					      "hosc",

					      &ccu_nm_ops,
@@ -223,7 +237,7 @@ static struct ccu_mux cpu_clk = { 
		.hw.init	= CLK_HW_INIT_PARENTS("cpu",

						      cpu_parents,

						      &ccu_mux_ops,

						      CLK_IS_CRITICAL),

						      CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),

	}

};
@@ -1021,9 +1035,9 @@ static struct ccu_common *sun4i_sun7i_ccu_clks[] = { 
	&out_b_clk.common

};



/* Post-divider for pll-audio is hardcoded to 4 */

/* Post-divider for pll-audio is hardcoded to 1 */

static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",

			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);

			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",

			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -1420,10 +1434,10 @@ static void __init sun4i_ccu_init(struct device_node *node, 
		return;

	}



	/* Force the PLL-Audio-1x divider to 4 */

	/* Force the PLL-Audio-1x divider to 1 */

	val = readl(reg + SUN4I_PLL_AUDIO_REG);

	val &= ~GENMASK(29, 26);

	writel(val | (4 << 26), reg + SUN4I_PLL_AUDIO_REG);

	writel(val | (1 << 26), reg + SUN4I_PLL_AUDIO_REG);



	/*

	 * Use the peripheral PLL6 as the AHB parent, instead of CPU /

drivers/clk/sunxi-ng/ccu-sun4i-a10.h

+2 −2
Original line number Diff line number Diff line
@@ -29,7 +29,7 @@ 
#define CLK_PLL_AUDIO_4X	6

#define CLK_PLL_AUDIO_8X	7

#define CLK_PLL_VIDEO0		8

#define CLK_PLL_VIDEO0_2X	9

/* The PLL_VIDEO0_2X clock is exported */

#define CLK_PLL_VE		10

#define CLK_PLL_DDR_BASE	11

#define CLK_PLL_DDR		12
@@ -38,7 +38,7 @@ 
#define CLK_PLL_PERIPH		15

#define CLK_PLL_PERIPH_SATA	16

#define CLK_PLL_VIDEO1		17

#define CLK_PLL_VIDEO1_2X	18

/* The PLL_VIDEO1_2X clock is exported */

#define CLK_PLL_GPU		19



/* The CPU clock is exported */

drivers/clk/sunxi-ng/ccu-sun5i.c

+20 −7
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ 
#include "ccu_nkmp.h"

#include "ccu_nm.h"

#include "ccu_phase.h"

#include "ccu_sdm.h"



#include "ccu-sun5i.h"
@@ -49,11 +50,20 @@ static struct ccu_nkmp pll_core_clk = { 
 * the base (2x, 4x and 8x), and one variable divider (the one true

 * pll audio).

 *

 * We don't have any need for the variable divider for now, so we just

 * hardcode it to match with the clock names

 * With sigma-delta modulation for fractional-N on the audio PLL,

 * we have to use specific dividers. This means the variable divider

 * can no longer be used, as the audio codec requests the exact clock

 * rates we support through this mechanism. So we now hard code the

 * variable divider to 1. This means the clock rates will no longer

 * match the clock names.

 */

#define SUN5I_PLL_AUDIO_REG	0x008



static struct ccu_sdm_setting pll_audio_sdm_table[] = {

	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },

	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },

};



static struct ccu_nm pll_audio_base_clk = {

	.enable		= BIT(31),

	.n		= _SUNXI_CCU_MULT_OFFSET(8, 7, 0),
@@ -63,8 +73,11 @@ static struct ccu_nm pll_audio_base_clk = { 
	 * offset

	 */

	.m		= _SUNXI_CCU_DIV_OFFSET(0, 5, 0),

	.sdm		= _SUNXI_CCU_SDM(pll_audio_sdm_table, 0,

					 0x00c, BIT(31)),

	.common		= {

		.reg		= 0x008,

		.features	= CCU_FEATURE_SIGMA_DELTA_MOD,

		.hw.init	= CLK_HW_INIT("pll-audio-base",

					      "hosc",

					      &ccu_nm_ops,
@@ -597,9 +610,9 @@ static struct ccu_common *sun5i_a10s_ccu_clks[] = { 
	&iep_clk.common,

};



/* We hardcode the divider to 4 for now */

/* We hardcode the divider to 1 for now */

static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",

			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);

			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",

			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -980,10 +993,10 @@ static void __init sun5i_ccu_init(struct device_node *node, 
		return;

	}



	/* Force the PLL-Audio-1x divider to 4 */

	/* Force the PLL-Audio-1x divider to 1 */

	val = readl(reg + SUN5I_PLL_AUDIO_REG);

	val &= ~GENMASK(19, 16);

	writel(val | (3 << 16), reg + SUN5I_PLL_AUDIO_REG);

	val &= ~GENMASK(29, 26);

	writel(val | (0 << 26), reg + SUN5I_PLL_AUDIO_REG);



	/*

	 * Use the peripheral PLL as the AHB parent, instead of CPU /

drivers/clk/sunxi-ng/ccu-sun6i-a31.c

+26 −14
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ 
#include "ccu_nkmp.h"

#include "ccu_nm.h"

#include "ccu_phase.h"

#include "ccu_sdm.h"



#include "ccu-sun6i-a31.h"
@@ -48,15 +49,26 @@ static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu", 
 * the base (2x, 4x and 8x), and one variable divider (the one true

 * pll audio).

 *

 * We don't have any need for the variable divider for now, so we just

 * hardcode it to match with the clock names

 * With sigma-delta modulation for fractional-N on the audio PLL,

 * we have to use specific dividers. This means the variable divider

 * can no longer be used, as the audio codec requests the exact clock

 * rates we support through this mechanism. So we now hard code the

 * variable divider to 1. This means the clock rates will no longer

 * match the clock names.

 */

#define SUN6I_A31_PLL_AUDIO_REG	0x008



static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",

static struct ccu_sdm_setting pll_audio_sdm_table[] = {

	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },

	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },

};



static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",

				       "osc24M", 0x008,

				       8, 7,	/* N */

				       0, 5,	/* M */

				       pll_audio_sdm_table, BIT(24),

				       0x284, BIT(31),

				       BIT(31),	/* gate */

				       BIT(28),	/* lock */

				       CLK_SET_RATE_UNGATE);
@@ -608,7 +620,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", lcd_ch1_parents, 
				 0x150, 0, 4, 24, 2, BIT(31),

				 CLK_SET_RATE_PARENT);



static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M", 0x150, BIT(30), 0);

static SUNXI_CCU_GATE(hdmi_ddc_clk, "ddc", "osc24M", 0x150, BIT(30), 0);



static SUNXI_CCU_GATE(ps_clk, "ps", "lcd1-ch1", 0x140, BIT(31), 0);
@@ -950,9 +962,9 @@ static struct ccu_common *sun6i_a31_ccu_clks[] = { 
	&out_c_clk.common,

};



/* We hardcode the divider to 4 for now */

/* We hardcode the divider to 1 for now */

static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",

			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);

			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",

			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);

static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
@@ -1221,10 +1233,10 @@ static void __init sun6i_a31_ccu_setup(struct device_node *node) 
		return;

	}



	/* Force the PLL-Audio-1x divider to 4 */

	/* Force the PLL-Audio-1x divider to 1 */

	val = readl(reg + SUN6I_A31_PLL_AUDIO_REG);

	val &= ~GENMASK(19, 16);

	writel(val | (3 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);

	writel(val | (0 << 16), reg + SUN6I_A31_PLL_AUDIO_REG);



	/* Force PLL-MIPI to MIPI mode */

	val = readl(reg + SUN6I_A31_PLL_MIPI_REG);