Merge "drivers: pinctrl: Add QUP macros for register read/write on kona" (ffa13ea5) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/pinctrl/qcom/pinctrl-kona.c

+21 −0

Original line number	Diff line number	Diff line
		@@ -113,6 +113,18 @@
		.intr_detection_bit = -1, \
		.intr_detection_width = -1, \
		}

		#define QUP_I3C_0_MODE_OFFSET 0x9BB000
		#define QUP_I3C_1_MODE_OFFSET 0x9BC000
		#define QUP_I3C_8_MODE_OFFSET 0x5BA000
		#define QUP_I3C_14_MODE_OFFSET 0x5BB000

		#define QUP_I3C(qup_mode, qup_offset) \
		{ \
		.mode = qup_mode, \
		.offset = qup_offset, \
		}

		static const struct pinctrl_pin_desc kona_pins[] = {
		PINCTRL_PIN(0, "GPIO_0"),
		PINCTRL_PIN(1, "GPIO_1"),
		@@ -1698,6 +1710,13 @@ static const struct msm_pingroup kona_groups[] = {
		[183] = UFS_RESET(ufs_reset, 0x5b8000),
		};

		static struct pinctrl_qup kona_qup_regs[] = {
		[0] = QUP_I3C(0, QUP_I3C_0_MODE_OFFSET),
		[1] = QUP_I3C(1, QUP_I3C_1_MODE_OFFSET),
		[2] = QUP_I3C(8, QUP_I3C_8_MODE_OFFSET),
		[3] = QUP_I3C(14, QUP_I3C_14_MODE_OFFSET),
		};

		static const struct msm_pinctrl_soc_data kona_pinctrl = {
		.pins = kona_pins,
		.npins = ARRAY_SIZE(kona_pins),
		@@ -1706,6 +1725,8 @@ static const struct msm_pinctrl_soc_data kona_pinctrl = {
		.groups = kona_groups,
		.ngroups = ARRAY_SIZE(kona_groups),
		.ngpios = 180,
		.qup_regs = kona_qup_regs,
		.nqup_regs = ARRAY_SIZE(kona_qup_regs),
		};

		static int kona_pinctrl_probe(struct platform_device *pdev)

drivers/pinctrl/qcom/pinctrl-msm.c

+39 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2013, Sony Mobile Communications AB.
		* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -31,6 +31,7 @@
		#include <linux/reboot.h>
		#include <linux/pm.h>
		#include <linux/log2.h>
		#include <linux/bitmap.h>

		#include "../core.h"
		#include "../pinconf.h"
		@@ -39,6 +40,7 @@

		#define MAX_NR_GPIO 300
		#define PS_HOLD_OFFSET 0x820
		#define QUP_MASK GENMASK(5, 0)

		/**
		* struct msm_pinctrl - state for a pinctrl-msm device
		@@ -1058,6 +1060,42 @@ static struct syscore_ops msm_pinctrl_pm_ops = {
		.resume = msm_pinctrl_resume,
		};

		int msm_qup_write(u32 mode, u32 val)
		{
		int i;
		struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs;
		int num_regs = msm_pinctrl_data->soc->nqup_regs;

		/Iterate over modes/
		for (i = 0; i < num_regs; i++) {
		if (regs[i].mode == mode) {
		writel_relaxed(val & QUP_MASK,
		msm_pinctrl_data->regs + regs[i].offset);
		return 0;
		}
		}

		return -ENOENT;
		}

		int msm_qup_read(unsigned int mode)
		{
		int i, val;
		struct pinctrl_qup *regs = msm_pinctrl_data->soc->qup_regs;
		int num_regs = msm_pinctrl_data->soc->nqup_regs;

		/Iterate over modes/
		for (i = 0; i < num_regs; i++) {
		if (regs[i].mode == mode) {
		val = readl_relaxed(msm_pinctrl_data->regs +
		regs[i].offset);
		return val & QUP_MASK;
		}
		}

		return -ENOENT;
		}

		int msm_pinctrl_probe(struct platform_device *pdev,
		const struct msm_pinctrl_soc_data *soc_data)
		{

drivers/pinctrl/qcom/pinctrl-msm.h

+14 −0

Original line number	Diff line number	Diff line
		@@ -13,6 +13,8 @@
		#ifndef __PINCTRL_MSM_H__
		#define __PINCTRL_MSM_H__

		#include <linux/pinctrl/qcom-pinctrl.h>

		struct pinctrl_pin_desc;

		/**
		@@ -99,6 +101,16 @@ struct msm_pingroup {
		unsigned intr_detection_width:5;
		};

		/*
		* struct pinctrl_qup - Qup mode configuration
		* @mode: Qup i3c mode
		* @offset: Offset of the register
		*/
		struct pinctrl_qup {
		u32 mode;
		u32 offset;
		};

		/**
		* struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
		* @pins: An array describing all pins the pin controller affects.
		@@ -119,6 +131,8 @@ struct msm_pinctrl_soc_data {
		unsigned ngroups;
		unsigned ngpios;
		bool pull_no_keeper;
		struct pinctrl_qup *qup_regs;
		unsigned int nqup_regs;
		};

		int msm_pinctrl_probe(struct platform_device *pdev,

include/linux/pinctrl/qcom-pinctrl.h

0 → 100644

+14 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2019, The Linux Foundation. All rights reserved.
		*/

		#ifndef __LINUX_PINCTRL_MSM_H__
		#define __LINUX_PINCTRL_MSM_H__

		/* APIS to access qup_i3c registers */
		int msm_qup_write(u32 mode, u32 val);
		int msm_qup_read(u32 mode);


		#endif /* __LINUX_PINCTRL_MSM_H__ */