Loading drivers/mmc/host/sdhci-msm.c +0 −6 Original line number Diff line number Diff line Loading @@ -156,7 +156,6 @@ /* 512 descriptors */ #define SDHCI_MSM_MAX_SEGMENTS (1 << 9) #define SDHCI_MSM_MMC_CLK_GATE_DELAY 200 /* msecs */ #define CORE_FREQ_100MHZ (100 * 1000 * 1000) #define TCXO_FREQ 19200000 Loading Loading @@ -5615,11 +5614,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) sdhci_msm_writel_relaxed(INT_MASK, host, msm_host_offset->CORE_PWRCTL_MASK); #ifdef CONFIG_MMC_CLKGATE /* Set clock gating delay to be used when CONFIG_MMC_CLKGATE is set */ msm_host->mmc->clkgate_delay = SDHCI_MSM_MMC_CLK_GATE_DELAY; #endif /* Set host capabilities */ msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width; msm_host->mmc->caps |= msm_host->pdata->caps; Loading drivers/mmc/host/sdhci.c +0 −7 Original line number Diff line number Diff line Loading @@ -64,16 +64,9 @@ static void sdhci_dump_state(struct sdhci_host *host) { struct mmc_host *mmc = host->mmc; #ifdef CONFIG_MMC_CLKGATE pr_info("%s: clk: %d clk-gated: %d claimer: %s pwr: %d host->irq = %d\n", mmc_hostname(mmc), host->clock, mmc->clk_gated, mmc->claimer->task->comm, host->pwr, (host->flags & SDHCI_HOST_IRQ_STATUS)); #else pr_info("%s: clk: %d claimer: %s pwr: %d\n", mmc_hostname(mmc), host->clock, mmc->claimer->task->comm, host->pwr); #endif pr_info("%s: rpmstatus[pltfm](runtime-suspend:usage_count:disable_depth)(%d:%d:%d)\n", mmc_hostname(mmc), mmc->parent->power.runtime_status, atomic_read(&mmc->parent->power.usage_count), Loading include/linux/mmc/host.h +0 −33 Original line number Diff line number Diff line Loading @@ -504,19 +504,6 @@ struct mmc_host { mmc_pm_flag_t pm_caps; /* supported pm features */ #ifdef CONFIG_MMC_CLKGATE int clk_requests; /* internal reference counter */ unsigned int clk_delay; /* number MCI clk hold cycles */ bool clk_gated; /* clock gated */ struct workqueue_struct *clk_gate_wq; /* clock gate work queue */ struct delayed_work clk_gate_work; /* delayed clock gate */ unsigned int clk_old; /* old clock value cache */ spinlock_t clk_lock; /* lock for clk fields */ struct mutex clk_gate_mutex; /* mutex for clock gating */ struct device_attribute clkgate_delay_attr; unsigned long clkgate_delay; #endif /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ unsigned short max_segs; /* see blk_queue_max_segments */ Loading Loading @@ -790,26 +777,6 @@ static inline void mmc_host_set_sdr104(struct mmc_host *host) host->caps |= MMC_CAP_UHS_SDR104; } #ifdef CONFIG_MMC_CLKGATE void mmc_host_clk_hold(struct mmc_host *host); void mmc_host_clk_release(struct mmc_host *host); unsigned int mmc_host_clk_rate(struct mmc_host *host); #else static inline void mmc_host_clk_hold(struct mmc_host *host) { } static inline void mmc_host_clk_release(struct mmc_host *host) { } static inline unsigned int mmc_host_clk_rate(struct mmc_host *host) { return host->ios.clock; } #endif static inline int mmc_card_hs(struct mmc_card *card) { return card->host->ios.timing == MMC_TIMING_SD_HS || Loading Loading
drivers/mmc/host/sdhci-msm.c +0 −6 Original line number Diff line number Diff line Loading @@ -156,7 +156,6 @@ /* 512 descriptors */ #define SDHCI_MSM_MAX_SEGMENTS (1 << 9) #define SDHCI_MSM_MMC_CLK_GATE_DELAY 200 /* msecs */ #define CORE_FREQ_100MHZ (100 * 1000 * 1000) #define TCXO_FREQ 19200000 Loading Loading @@ -5615,11 +5614,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) sdhci_msm_writel_relaxed(INT_MASK, host, msm_host_offset->CORE_PWRCTL_MASK); #ifdef CONFIG_MMC_CLKGATE /* Set clock gating delay to be used when CONFIG_MMC_CLKGATE is set */ msm_host->mmc->clkgate_delay = SDHCI_MSM_MMC_CLK_GATE_DELAY; #endif /* Set host capabilities */ msm_host->mmc->caps |= msm_host->pdata->mmc_bus_width; msm_host->mmc->caps |= msm_host->pdata->caps; Loading
drivers/mmc/host/sdhci.c +0 −7 Original line number Diff line number Diff line Loading @@ -64,16 +64,9 @@ static void sdhci_dump_state(struct sdhci_host *host) { struct mmc_host *mmc = host->mmc; #ifdef CONFIG_MMC_CLKGATE pr_info("%s: clk: %d clk-gated: %d claimer: %s pwr: %d host->irq = %d\n", mmc_hostname(mmc), host->clock, mmc->clk_gated, mmc->claimer->task->comm, host->pwr, (host->flags & SDHCI_HOST_IRQ_STATUS)); #else pr_info("%s: clk: %d claimer: %s pwr: %d\n", mmc_hostname(mmc), host->clock, mmc->claimer->task->comm, host->pwr); #endif pr_info("%s: rpmstatus[pltfm](runtime-suspend:usage_count:disable_depth)(%d:%d:%d)\n", mmc_hostname(mmc), mmc->parent->power.runtime_status, atomic_read(&mmc->parent->power.usage_count), Loading
include/linux/mmc/host.h +0 −33 Original line number Diff line number Diff line Loading @@ -504,19 +504,6 @@ struct mmc_host { mmc_pm_flag_t pm_caps; /* supported pm features */ #ifdef CONFIG_MMC_CLKGATE int clk_requests; /* internal reference counter */ unsigned int clk_delay; /* number MCI clk hold cycles */ bool clk_gated; /* clock gated */ struct workqueue_struct *clk_gate_wq; /* clock gate work queue */ struct delayed_work clk_gate_work; /* delayed clock gate */ unsigned int clk_old; /* old clock value cache */ spinlock_t clk_lock; /* lock for clk fields */ struct mutex clk_gate_mutex; /* mutex for clock gating */ struct device_attribute clkgate_delay_attr; unsigned long clkgate_delay; #endif /* host specific block data */ unsigned int max_seg_size; /* see blk_queue_max_segment_size */ unsigned short max_segs; /* see blk_queue_max_segments */ Loading Loading @@ -790,26 +777,6 @@ static inline void mmc_host_set_sdr104(struct mmc_host *host) host->caps |= MMC_CAP_UHS_SDR104; } #ifdef CONFIG_MMC_CLKGATE void mmc_host_clk_hold(struct mmc_host *host); void mmc_host_clk_release(struct mmc_host *host); unsigned int mmc_host_clk_rate(struct mmc_host *host); #else static inline void mmc_host_clk_hold(struct mmc_host *host) { } static inline void mmc_host_clk_release(struct mmc_host *host) { } static inline unsigned int mmc_host_clk_rate(struct mmc_host *host) { return host->ios.clock; } #endif static inline int mmc_card_hs(struct mmc_card *card) { return card->host->ios.timing == MMC_TIMING_SD_HS || Loading