Commit fee0fddc authored Mar 01, 2018 by Imre Deak

drm/i915/gen9, gen10: Disable FBC on planes with a misaligned Y-offset



Enabling FBC on a plane having a Y-offset that isn't divisible by 4 may
cause pipe FIFO underruns and flickers, so disable FBC on such a config.

I tried the followings to work around the issue:
- enable each HW work around in ILK_DPFC_CHICKEN
- disable each compression algorithm in ILK_DPFC_CONTROL
- disable low-power watermarks
None of the above got rid of the problem. I haven't found this issue in
the Bspec/WA database either.

Besides the igt testcase below (yet to be merged) an easy way to
reproduce the issue is to enable a plane with FBC and a plane Y-offset
not aligned to 4 and then just enable/disable FBC in a loop, keeping the
plane enabled.

I could trigger the problem on BXT/GLK/SKL/CNL, so assume for now that it's
only present on GEN9 and GEN10.

v2: (Ville)
- Run the test/apply the WA on CNL as well.
- Use IS_GEN() instead of INTEL_GEN().
- Fix spelling.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Testcase: igt/kms_plane/plane-clipping-pipe-A-planes
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180301134457.13974-1-imre.deak@intel.com

parent c27557ab

drivers/gpu/drm/i915/intel_fbc.c

+11 −0

Original line number	Diff line number	Diff line
		@@ -859,6 +859,17 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
		return false;
		}

		/*
		* Work around a problem on GEN9+ HW, where enabling FBC on a plane
		* having a Y offset that isn't divisible by 4 causes FIFO underrun
		* and screen flicker.
		*/
		if (IS_GEN(dev_priv, 9, 10) &&
		(fbc->state_cache.plane.adjusted_y & 3)) {
		fbc->no_fbc_reason = "plane Y offset is misaligned";
		return false;
		}

		return true;
		}