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Commit fec9181c authored by Eugeni Dodonov's avatar Eugeni Dodonov Committed by Daniel Vetter
Browse files

drm/i915: add port clock selection support for HSW 



Multiple clocks can drive different outputs.

v2: use the port enums to access individual ports

v1 Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
Signed-off-by: default avatarEugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e93ea06a

drivers/gpu/drm/i915/i915_reg.h

+23 −0
Original line number Original line Diff line number Diff line
@@ -4142,4 +4142,27 @@ 
#define  SPLL_PLL_FREQ_810MHz	(0<<26)

#define  SPLL_PLL_FREQ_810MHz	(0<<26)

#define  SPLL_PLL_FREQ_1350MHz	(1<<26)

#define  SPLL_PLL_FREQ_1350MHz	(1<<26)





/* Port clock selection */

#define PORT_CLK_SEL_A			0x46100

#define PORT_CLK_SEL_B			0x46104

#define PORT_CLK_SEL(port) _PORT(port, \

					PORT_CLK_SEL_A, \

					PORT_CLK_SEL_B)

#define  PORT_CLK_SEL_LCPLL_2700	(0<<29)

#define  PORT_CLK_SEL_LCPLL_1350	(1<<29)

#define  PORT_CLK_SEL_LCPLL_810		(2<<29)

#define  PORT_CLK_SEL_SPLL			(3<<29)

#define  PORT_CLK_SEL_WRPLL1		(4<<29)

#define  PORT_CLK_SEL_WRPLL2		(5<<29)



/* Pipe clock selection */

#define PIPE_CLK_SEL_A			0x46140

#define PIPE_CLK_SEL_B			0x46144

#define PIPE_CLK_SEL(pipe) _PIPE(pipe, \

					PIPE_CLK_SEL_A, \

					PIPE_CLK_SEL_B)

/* For each pipe, we need to select the corresponding port clock */

#define  PIPE_CLK_SEL_DISABLED	(0x0<<29)

#define  PIPE_CLK_SEL_PORT(x)	((x+1)<<29)



#endif /* _I915_REG_H_ */
 
#endif /* _I915_REG_H_ */