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Commit fe604b52 authored by Tatenda Chipeperekwa's avatar Tatenda Chipeperekwa
Browse files

clk: qcom: msm: update VDD levels for DisplayPort clocks on KONA 



Update the VDD levels as per the previously validated values
from the clock frequency plan.

Change-Id: I096971e4798cbc017e0702a99908b4940dbe8a2d
Signed-off-by: default avatarTatenda Chipeperekwa <tatendac@codeaurora.org>
parent b451b394

drivers/clk/qcom/dispcc-kona.c

+9 −5
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/* Copyright (c) 2018, The Linux Foundation. All rights reserved. */

/* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */



#define pr_fmt(fmt) "clk: %s: " fmt, __func__
@@ -553,7 +553,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto1_clk_src = { 
		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 12800,

			[VDD_LOWER] = 180000,

			[VDD_LOWER] = 108000,

			[VDD_LOW] = 180000,

			[VDD_LOW_L1] = 360000,

			[VDD_NOMINAL] = 540000},

	},
@@ -575,7 +576,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = { 
		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 12800,

			[VDD_LOWER] = 180000,

			[VDD_LOWER] = 108000,

			[VDD_LOW] = 180000,

			[VDD_LOW_L1] = 360000,

			[VDD_NOMINAL] = 540000},

	},
@@ -605,7 +607,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = { 
		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 270000,

			[VDD_LOWER] = 162000,

			[VDD_LOW] = 270000,

			[VDD_LOW_L1] = 540000,

			[VDD_NOMINAL] = 810000},

	},
@@ -627,7 +630,8 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = { 
		.num_rate_max = VDD_NUM,

		.rate_max = (unsigned long[VDD_NUM]) {

			[VDD_MIN] = 19200,

			[VDD_LOWER] = 270000,

			[VDD_LOWER] = 162000,

			[VDD_LOW] = 270000,

			[VDD_LOW_L1] = 540000,

			[VDD_NOMINAL] = 810000},

	},