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Commit fe56cf45 authored by Jesse Barnes's avatar Jesse Barnes Committed by Dave Airlie
Browse files

drm: Fix ordering of bit fields in EDID structure leading huge vsync values.

parent c8766ac5
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+2 −2
Original line number Diff line number Diff line
@@ -58,10 +58,10 @@ struct detailed_pixel_timing {
	u8 hsync_pulse_width_lo;
	u8 vsync_pulse_width_lo:4;
	u8 vsync_offset_lo:4;
	u8 hsync_pulse_width_hi:2;
	u8 hsync_offset_hi:2;
	u8 vsync_pulse_width_hi:2;
	u8 vsync_offset_hi:2;
	u8 hsync_pulse_width_hi:2;
	u8 hsync_offset_hi:2;
	u8 width_mm_lo;
	u8 height_mm_lo;
	u8 height_mm_hi:4;