Loading arch/mips/kernel/smtc.c +0 −2 Original line number Diff line number Diff line Loading @@ -28,8 +28,6 @@ * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. */ #define MIPS_CPU_IPI_IRQ 1 #define LOCK_MT_PRA() \ local_irq_save(flags); \ mtflags = dmt() Loading include/asm-mips/smtc.h +10 −0 Original line number Diff line number Diff line Loading @@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t); #define PARKED_INDEX ((unsigned int)0x80000000) /* * Define low-level interrupt mask for IPIs, if necessary. * By default, use SW interrupt 1, which requires no external * hardware support, but which works only for single-core * MIPS MT systems. */ #ifndef MIPS_CPU_IPI_IRQ #define MIPS_CPU_IPI_IRQ 1 #endif #endif /* _ASM_SMTC_MT_H */ Loading
arch/mips/kernel/smtc.c +0 −2 Original line number Diff line number Diff line Loading @@ -28,8 +28,6 @@ * This file should be built into the kernel only if CONFIG_MIPS_MT_SMTC is set. */ #define MIPS_CPU_IPI_IRQ 1 #define LOCK_MT_PRA() \ local_irq_save(flags); \ mtflags = dmt() Loading
include/asm-mips/smtc.h +10 −0 Original line number Diff line number Diff line Loading @@ -55,4 +55,14 @@ extern void smtc_boot_secondary(int cpu, struct task_struct *t); #define PARKED_INDEX ((unsigned int)0x80000000) /* * Define low-level interrupt mask for IPIs, if necessary. * By default, use SW interrupt 1, which requires no external * hardware support, but which works only for single-core * MIPS MT systems. */ #ifndef MIPS_CPU_IPI_IRQ #define MIPS_CPU_IPI_IRQ 1 #endif #endif /* _ASM_SMTC_MT_H */