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Commit fe440293 authored by Chris Wilson's avatar Chris Wilson
Browse files

Merge branch 'drm-intel-fixes' into drm-intel-next 

Apply the SandyBridge stability fixes from -fixes.
parents 417ae147 4efe0708

drivers/gpu/drm/i915/i915_reg.h

+6 −0
Original line number Diff line number Diff line
@@ -513,6 +513,10 @@ 
#define   GEN6_BLITTER_SYNC_STATUS			(1 << 24)

#define   GEN6_BLITTER_USER_INTERRUPT			(1 << 22)



#define GEN6_BLITTER_ECOSKPD	0x221d0

#define   GEN6_BLITTER_LOCK_SHIFT			16

#define   GEN6_BLITTER_FBC_NOTIFY			(1<<3)



#define GEN6_BSD_SLEEP_PSMI_CONTROL	0x12050

#define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK	(1 << 16)

#define   GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE		(1 << 0)
@@ -2631,6 +2635,8 @@ 
#define DISPLAY_PORT_PLL_BIOS_2         0x46014



#define PCH_DSPCLK_GATE_D	0x42020

# define DPFCUNIT_CLOCK_GATE_DISABLE		(1 << 9)

# define DPFCRUNIT_CLOCK_GATE_DISABLE		(1 << 8)

# define DPFDUNIT_CLOCK_GATE_DISABLE		(1 << 7)

# define DPARBUNIT_CLOCK_GATE_DISABLE		(1 << 5)

drivers/gpu/drm/i915/intel_display.c

+24 −1
Original line number Diff line number Diff line
@@ -1718,6 +1718,26 @@ static bool g4x_fbc_enabled(struct drm_device *dev) 
	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;

}



static void sandybridge_blit_fbc_update(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 blt_ecoskpd;



	/* Make sure blitter notifies FBC of writes */

	__gen6_force_wake_get(dev_priv);

	blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);

	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<

		GEN6_BLITTER_LOCK_SHIFT;

	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

	blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;

	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

	blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<

			 GEN6_BLITTER_LOCK_SHIFT);

	I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);

	POSTING_READ(GEN6_BLITTER_ECOSKPD);

	__gen6_force_wake_put(dev_priv);

}



static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)

{

	struct drm_device *dev = crtc->dev;
@@ -1771,6 +1791,7 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 
		I915_WRITE(SNB_DPFC_CTL_SA,

			   SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);

		I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);

		sandybridge_blit_fbc_update(dev);

	}



	DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
@@ -6818,7 +6839,9 @@ void intel_enable_clock_gating(struct drm_device *dev) 


		if (IS_GEN5(dev)) {

			/* Required for FBC */

			dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;

			dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |

				DPFCRUNIT_CLOCK_GATE_DISABLE |

				DPFDUNIT_CLOCK_GATE_DISABLE;

			/* Required for CxSR */

			dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;