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Commit fdf41815 authored by Bjorn Helgaas's avatar Bjorn Helgaas Committed by Greg Kroah-Hartman
Browse files

drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions 

[ Upstream commit 35e768e296729ac96a8c33b7810b6cb1673ae961 ]

Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2
definitions.  No functional change intended.

Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org


Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Stable-dep-of: ce7d88110b9e ("drm/amdgpu: Use RMW accessors for changing LNKCTL")
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 071dc77d

drivers/gpu/drm/amd/amdgpu/cik.c

+14 −8
Original line number Diff line number Diff line
@@ -1491,13 +1491,19 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 


				/* linkctl2 */

				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);



				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



				tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
@@ -1514,13 +1520,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) 
	WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~0xf;

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;

	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

		tmp16 |= 3; /* gen3 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)

		tmp16 |= 2; /* gen2 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= 1; /* gen1 */

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);

drivers/gpu/drm/amd/amdgpu/si.c

+14 −8
Original line number Diff line number Diff line
@@ -1662,13 +1662,19 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);



				pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (bridge_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);



				pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

				tmp16 &= ~((1 << 4) | (7 << 7));

				tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));

				tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN);

				tmp16 |= (gpu_cfg2 &

					  (PCI_EXP_LNKCTL2_ENTER_COMP |

					   PCI_EXP_LNKCTL2_TX_MARGIN));

				pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



				tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -1683,13 +1689,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev) 
	WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);



	pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);

	tmp16 &= ~0xf;

	tmp16 &= ~PCI_EXP_LNKCTL2_TLS;

	if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)

		tmp16 |= 3;

		tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */

	else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)

		tmp16 |= 2;

		tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */

	else

		tmp16 |= 1;

		tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */

	pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);



	speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);