Loading arch/arm/mach-omap2/clockdomain.c +0 −8 Original line number Diff line number Diff line Loading @@ -1224,14 +1224,6 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) return 0; } u32 clkdm_xlate_address(struct clockdomain *clkdm) { if (arch_clkdm->clkdm_xlate_address) return arch_clkdm->clkdm_xlate_address(clkdm); return 0; } /** * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm * @clkdm: struct clockdomain * Loading arch/arm/mach-omap2/clockdomain.h +0 −2 Original line number Diff line number Diff line Loading @@ -175,7 +175,6 @@ struct clkdm_ops { void (*clkdm_deny_idle)(struct clockdomain *clkdm); int (*clkdm_clk_enable)(struct clockdomain *clkdm); int (*clkdm_clk_disable)(struct clockdomain *clkdm); u32 (*clkdm_xlate_address)(struct clockdomain *clkdm); }; int clkdm_register_platform_funcs(struct clkdm_ops *co); Loading Loading @@ -214,7 +213,6 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); u32 clkdm_xlate_address(struct clockdomain *clkdm); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); Loading arch/arm/mach-omap2/cm.h +3 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl * @module_enable: ptr to the SoC CM-specific module_enable impl * @module_disable: ptr to the SoC CM-specific module_disable impl * @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl */ struct cm_ll_data { int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, Loading @@ -62,6 +63,7 @@ struct cm_ll_data { u8 idlest_shift); void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs); u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs); }; extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, Loading @@ -72,6 +74,7 @@ int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg, u8 idlest_shift); int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs); extern int cm_register(const struct cm_ll_data *cld); extern int cm_unregister(const struct cm_ll_data *cld); int omap_cm_init(void); Loading arch/arm/mach-omap2/cm33xx.c +6 −0 Original line number Diff line number Diff line Loading @@ -333,6 +333,11 @@ static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) return 0; } static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset) { return cm_base.pa + inst + offset; } struct clkdm_ops am33xx_clkdm_operations = { .clkdm_sleep = am33xx_clkdm_sleep, .clkdm_wakeup = am33xx_clkdm_wakeup, Loading @@ -347,6 +352,7 @@ static const struct cm_ll_data am33xx_cm_ll_data = { .wait_module_idle = &am33xx_cm_wait_module_idle, .module_enable = &am33xx_cm_module_enable, .module_disable = &am33xx_cm_module_disable, .xlate_clkctrl = &am33xx_cm_xlate_clkctrl, }; int __init am33xx_cm_init(const struct omap_prcm_init_data *data) Loading arch/arm/mach-omap2/cm_common.c +10 −0 Original line number Diff line number Diff line Loading @@ -175,6 +175,16 @@ int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) return 0; } u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) { if (!cm_ll_data->xlate_clkctrl) { WARN_ONCE(1, "cm: %s: no low-level function defined\n", __func__); return 0; } return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs); } /** * cm_register - register per-SoC low-level data with the CM * @cld: low-level per-SoC OMAP CM data & function pointers to register Loading Loading
arch/arm/mach-omap2/clockdomain.c +0 −8 Original line number Diff line number Diff line Loading @@ -1224,14 +1224,6 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk) return 0; } u32 clkdm_xlate_address(struct clockdomain *clkdm) { if (arch_clkdm->clkdm_xlate_address) return arch_clkdm->clkdm_xlate_address(clkdm); return 0; } /** * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm * @clkdm: struct clockdomain * Loading
arch/arm/mach-omap2/clockdomain.h +0 −2 Original line number Diff line number Diff line Loading @@ -175,7 +175,6 @@ struct clkdm_ops { void (*clkdm_deny_idle)(struct clockdomain *clkdm); int (*clkdm_clk_enable)(struct clockdomain *clkdm); int (*clkdm_clk_disable)(struct clockdomain *clkdm); u32 (*clkdm_xlate_address)(struct clockdomain *clkdm); }; int clkdm_register_platform_funcs(struct clkdm_ops *co); Loading Loading @@ -214,7 +213,6 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh); int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh); u32 clkdm_xlate_address(struct clockdomain *clkdm); extern void __init omap242x_clockdomains_init(void); extern void __init omap243x_clockdomains_init(void); Loading
arch/arm/mach-omap2/cm.h +3 −0 Original line number Diff line number Diff line Loading @@ -52,6 +52,7 @@ extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl * @module_enable: ptr to the SoC CM-specific module_enable impl * @module_disable: ptr to the SoC CM-specific module_disable impl * @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl */ struct cm_ll_data { int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, Loading @@ -62,6 +63,7 @@ struct cm_ll_data { u8 idlest_shift); void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs); u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs); }; extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, Loading @@ -72,6 +74,7 @@ int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg, u8 idlest_shift); int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs); extern int cm_register(const struct cm_ll_data *cld); extern int cm_unregister(const struct cm_ll_data *cld); int omap_cm_init(void); Loading
arch/arm/mach-omap2/cm33xx.c +6 −0 Original line number Diff line number Diff line Loading @@ -333,6 +333,11 @@ static int am33xx_clkdm_clk_disable(struct clockdomain *clkdm) return 0; } static u32 am33xx_cm_xlate_clkctrl(u8 part, u16 inst, u16 offset) { return cm_base.pa + inst + offset; } struct clkdm_ops am33xx_clkdm_operations = { .clkdm_sleep = am33xx_clkdm_sleep, .clkdm_wakeup = am33xx_clkdm_wakeup, Loading @@ -347,6 +352,7 @@ static const struct cm_ll_data am33xx_cm_ll_data = { .wait_module_idle = &am33xx_cm_wait_module_idle, .module_enable = &am33xx_cm_module_enable, .module_disable = &am33xx_cm_module_disable, .xlate_clkctrl = &am33xx_cm_xlate_clkctrl, }; int __init am33xx_cm_init(const struct omap_prcm_init_data *data) Loading
arch/arm/mach-omap2/cm_common.c +10 −0 Original line number Diff line number Diff line Loading @@ -175,6 +175,16 @@ int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) return 0; } u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs) { if (!cm_ll_data->xlate_clkctrl) { WARN_ONCE(1, "cm: %s: no low-level function defined\n", __func__); return 0; } return cm_ll_data->xlate_clkctrl(part, inst, clkctrl_offs); } /** * cm_register - register per-SoC low-level data with the CM * @cld: low-level per-SoC OMAP CM data & function pointers to register Loading