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Commit fdc5714c authored by Da Hoon Pyun's avatar Da Hoon Pyun
Browse files

msm: npu: Support cx ipeak limit management 



This change is to support cx ipeak limit management in order to
allow sysmon to limit cx currrent by adjusting npu power level.

Change-Id: I98cfdd1a27e13fc69151f077ffc38f50405b95c2
Signed-off-by: default avatarDa Hoon Pyun <dpyun@codeaurora.org>
parent 9f6b4236

drivers/media/platform/msm/npu/npu_common.h

+2 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _NPU_COMMON_H
@@ -341,5 +341,5 @@ int load_fw(struct npu_device *npu_dev); 
int unload_fw(struct npu_device *npu_dev);

int npu_set_bw(struct npu_device *npu_dev, int new_ib, int new_ab);

int npu_process_kevent(struct npu_client *client, struct npu_kevent *kevt);



int npu_notify_cdsprm_cxlimit_activity(struct npu_device *npu_dev, bool enable);

#endif /* _NPU_COMMON_H */

drivers/media/platform/msm/npu/npu_dev.c

+194 −1
Original line number Diff line number Diff line
@@ -17,6 +17,7 @@ 
#include <linux/regulator/consumer.h>

#include <linux/thermal.h>

#include <linux/soc/qcom/llcc-qcom.h>

#include <linux/soc/qcom/cdsprm_cxlimit.h>

#include <soc/qcom/devfreq_devbw.h>



#include "npu_common.h"
@@ -111,7 +112,8 @@ static int npu_pm_suspend(struct device *dev); 
static int npu_pm_resume(struct device *dev);

static int __init npu_init(void);

static void __exit npu_exit(void);



static uint32_t npu_notify_cdsprm_cxlimit_corner(struct npu_device *npu_dev,

	uint32_t pwr_lvl);

/* -------------------------------------------------------------------------

 * File Scope Variables

 * -------------------------------------------------------------------------
@@ -387,6 +389,168 @@ static ssize_t boot_store(struct device *dev, 
 * Power Related

 * -------------------------------------------------------------------------

 */

static enum npu_power_level cdsprm_corner_to_npu_power_level(

	enum cdsprm_npu_corner corner)

{

	enum npu_power_level pwr_lvl = NPU_PWRLEVEL_TURBO_L1;



	switch (corner) {

	case CDSPRM_NPU_CLK_OFF:

		pwr_lvl = NPU_PWRLEVEL_OFF;

		break;

	case CDSPRM_NPU_MIN_SVS:

		pwr_lvl = NPU_PWRLEVEL_MINSVS;

		break;

	case CDSPRM_NPU_LOW_SVS:

		pwr_lvl = NPU_PWRLEVEL_LOWSVS;

		break;

	case CDSPRM_NPU_SVS:

		pwr_lvl = NPU_PWRLEVEL_SVS;

		break;

	case CDSPRM_NPU_SVS_L1:

		pwr_lvl = NPU_PWRLEVEL_SVS_L1;

		break;

	case CDSPRM_NPU_NOM:

		pwr_lvl = NPU_PWRLEVEL_NOM;

		break;

	case CDSPRM_NPU_NOM_L1:

		pwr_lvl = NPU_PWRLEVEL_NOM_L1;

		break;

	case CDSPRM_NPU_TURBO:

		pwr_lvl = NPU_PWRLEVEL_TURBO;

		break;

	case CDSPRM_NPU_TURBO_L1:

	default:

		pwr_lvl = NPU_PWRLEVEL_TURBO_L1;

		break;

	}



	return pwr_lvl;

}



static enum cdsprm_npu_corner npu_power_level_to_cdsprm_corner(

	enum npu_power_level pwr_lvl)

{

	enum cdsprm_npu_corner corner = CDSPRM_NPU_MIN_SVS;



	switch (pwr_lvl) {

	case NPU_PWRLEVEL_OFF:

		corner = CDSPRM_NPU_CLK_OFF;

		break;

	case NPU_PWRLEVEL_MINSVS:

		corner = CDSPRM_NPU_MIN_SVS;

		break;

	case NPU_PWRLEVEL_LOWSVS:

		corner = CDSPRM_NPU_LOW_SVS;

		break;

	case NPU_PWRLEVEL_SVS:

		corner = CDSPRM_NPU_SVS;

		break;

	case NPU_PWRLEVEL_SVS_L1:

		corner = CDSPRM_NPU_SVS_L1;

		break;

	case NPU_PWRLEVEL_NOM:

		corner = CDSPRM_NPU_NOM;

		break;

	case NPU_PWRLEVEL_NOM_L1:

		corner = CDSPRM_NPU_NOM_L1;

		break;

	case NPU_PWRLEVEL_TURBO:

		corner = CDSPRM_NPU_TURBO;

		break;

	case NPU_PWRLEVEL_TURBO_L1:

	default:

		corner = CDSPRM_NPU_TURBO_L1;

		break;

	}



	return corner;

}



static int npu_set_cdsprm_corner_limit(enum cdsprm_npu_corner corner)

{

	struct npu_pwrctrl *pwr;

	enum npu_power_level pwr_lvl;



	if (!g_npu_dev)

		return 0;



	pwr = &g_npu_dev->pwrctrl;

	pwr_lvl = cdsprm_corner_to_npu_power_level(corner);

	pwr->cdsprm_pwrlevel = pwr_lvl;

	NPU_DBG("power level from cdsp %d\n", pwr_lvl);



	return npu_set_power_level(g_npu_dev, false);

}



const struct cdsprm_npu_limit_cbs cdsprm_npu_limit_cbs = {

	.set_corner_limit = npu_set_cdsprm_corner_limit,

};



int npu_notify_cdsprm_cxlimit_activity(struct npu_device *npu_dev, bool enable)

{

	if (!npu_dev->cxlimit_registered)

		return 0;



	NPU_DBG("notify cxlimit %s activity\n", enable ? "enable" : "disable");



	return cdsprm_cxlimit_npu_activity_notify(enable ? 1 : 0);

}



static uint32_t npu_notify_cdsprm_cxlimit_corner(

	struct npu_device *npu_dev, uint32_t pwr_lvl)

{

	uint32_t corner, pwr_lvl_to_set;



	if (!npu_dev->cxlimit_registered)

		return pwr_lvl;



	corner = npu_power_level_to_cdsprm_corner(pwr_lvl);

	corner = cdsprm_cxlimit_npu_corner_notify(corner);

	pwr_lvl_to_set = cdsprm_corner_to_npu_power_level(corner);

	NPU_DBG("Notify cdsprm %d:%d\n", pwr_lvl,

			pwr_lvl_to_set);



	return pwr_lvl_to_set;

}



int npu_cdsprm_cxlimit_init(struct npu_device *npu_dev)

{

	bool enabled;

	int ret = 0;



	enabled = of_property_read_bool(npu_dev->pdev->dev.of_node,

		"qcom,npu-cxlimit-enable");

	NPU_DBG("qcom,npu-xclimit-enable is %s\n", enabled ? "true" : "false");



	npu_dev->cxlimit_registered = false;

	if (enabled) {

		ret = cdsprm_cxlimit_npu_limit_register(&cdsprm_npu_limit_cbs);

		if (ret) {

			NPU_ERR("register cxlimit npu limit failed\n");

		} else {

			NPU_DBG("register cxlimit npu limit succeeds\n");

			npu_dev->cxlimit_registered = true;

		}

	}



	return ret;

}



int npu_cdsprm_cxlimit_deinit(struct npu_device *npu_dev)

{

	int ret = 0;



	if (npu_dev->cxlimit_registered) {

		ret = cdsprm_cxlimit_npu_limit_deregister();

		if (ret)

			NPU_ERR("deregister cxlimit npu limit failed\n");

		npu_dev->cxlimit_registered = false;

	}



	return ret;

}



int npu_enable_core_power(struct npu_device *npu_dev)

{

	struct npu_pwrctrl *pwr = &npu_dev->pwrctrl;
@@ -530,6 +694,11 @@ int npu_set_power_level(struct npu_device *npu_dev, bool notify_cxlimit) 
		return 0;

	}



	/* notify cxlimit to get allowed power level */

	if ((pwr_level_to_set > pwr->active_pwrlevel) && notify_cxlimit)

		pwr_level_to_set = npu_notify_cdsprm_cxlimit_corner(

					npu_dev, pwr_level_to_cdsprm);



	pwr_level_to_set = min(pwr_level_to_set,

		npu_dev->pwrctrl.cdsprm_pwrlevel);
@@ -596,6 +765,12 @@ int npu_set_power_level(struct npu_device *npu_dev, bool notify_cxlimit) 
		ret = 0;

	}



	if ((pwr_level_to_cdsprm < pwr->active_pwrlevel) && notify_cxlimit) {

		npu_notify_cdsprm_cxlimit_corner(npu_dev,

			pwr_level_to_cdsprm);

		NPU_DBG("Notify cdsprm(post) %d\n", pwr_level_to_cdsprm);

	}



	pwr->active_pwrlevel = pwr_level_to_set;

	return ret;

}
@@ -708,6 +883,13 @@ static int npu_enable_clocks(struct npu_device *npu_dev, bool post_pil) 
	uint32_t pwrlevel_to_set, pwrlevel_idx;



	pwrlevel_to_set = pwr->active_pwrlevel;

	if (!post_pil) {

		pwrlevel_to_set = npu_notify_cdsprm_cxlimit_corner(

			npu_dev, pwrlevel_to_set);

		NPU_DBG("Notify cdsprm %d\n", pwrlevel_to_set);

		pwr->active_pwrlevel = pwrlevel_to_set;

	}



	pwrlevel_idx = npu_power_level_to_index(npu_dev, pwrlevel_to_set);

	pwrlevel = &pwr->pwrlevels[pwrlevel_idx];

	for (i = 0; i < npu_dev->core_clk_num; i++) {
@@ -775,6 +957,11 @@ static void npu_disable_clocks(struct npu_device *npu_dev, bool post_pil) 
	int i, rc = 0;

	struct npu_clk *core_clks = npu_dev->core_clks;



	if (!post_pil) {

		npu_notify_cdsprm_cxlimit_corner(npu_dev, NPU_PWRLEVEL_OFF);

		NPU_DBG("Notify cdsprm clock off\n");

	}



	for (i = npu_dev->core_clk_num - 1; i >= 0 ; i--) {

		if (post_pil) {

			if (!npu_is_post_clock(core_clks[i].clk_name))
@@ -2459,10 +2646,15 @@ static int npu_probe(struct platform_device *pdev) 
		thermal_cdev_update(tcdev);

	}



	rc = npu_cdsprm_cxlimit_init(npu_dev);

	if (rc)

		goto error_driver_init;



	g_npu_dev = npu_dev;



	return rc;

error_driver_init:

	npu_cdsprm_cxlimit_deinit(npu_dev);

	if (npu_dev->tcdev)

		thermal_cooling_device_unregister(npu_dev->tcdev);

	sysfs_remove_group(&npu_dev->device->kobj, &npu_fs_attr_group);
@@ -2487,6 +2679,7 @@ static int npu_remove(struct platform_device *pdev) 
	npu_dev = platform_get_drvdata(pdev);

	npu_host_deinit(npu_dev);

	npu_debugfs_deinit(npu_dev);

	npu_cdsprm_cxlimit_deinit(npu_dev);

	if (npu_dev->tcdev)

		thermal_cooling_device_unregister(npu_dev->tcdev);

	sysfs_remove_group(&npu_dev->device->kobj, &npu_fs_attr_group);

drivers/media/platform/msm/npu/npu_mgr.c

+6 −0
Original line number Diff line number Diff line
@@ -2697,6 +2697,9 @@ int32_t npu_host_exec_network_v2(struct npu_client *client, 
		return -EINVAL;

	}



	if (atomic_inc_return(&host_ctx->network_execute_cnt) == 1)

		npu_notify_cdsprm_cxlimit_activity(npu_dev, true);



	if (!network->is_active) {

		NPU_ERR("network is not active\n");

		ret = -EINVAL;
@@ -2847,6 +2850,9 @@ int32_t npu_host_exec_network_v2(struct npu_client *client, 
		host_error_hdlr(npu_dev, true);

	}



	if (atomic_dec_return(&host_ctx->network_execute_cnt) == 0)

		npu_notify_cdsprm_cxlimit_activity(npu_dev, false);



	return ret;

}

drivers/media/platform/msm/npu/npu_mgr.h

+1 −1
Original line number Diff line number Diff line
@@ -126,7 +126,7 @@ struct npu_host_ctx { 
	uint32_t fw_dbg_mode;

	uint32_t exec_flags_override;

	atomic_t ipc_trans_id;

	atomic_t network_exeute_cnt;

	atomic_t network_execute_cnt;



	uint32_t err_irq_sts;

	uint32_t wdg_irq_sts;