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Commit fcf8ab69 authored by Thomas Gleixner's avatar Thomas Gleixner
Browse files

Merge tag 'gic-4.4' of... 

Merge tag 'gic-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core

GIC updates for Linux 4.4 from Marc Zyngier:

- Enable basic GICv3 support on 32bit ARM (mostly for running VMs with
  more than 8 virtual CPUs)
- arm64 changes to deal with firmware limitations that forces a GICv3
  to be used as a GICv2
- A GICv2m erratum workaround on Applied Micro X-Gene2
parents 0e841b04 4f64cb65

Documentation/arm64/booting.txt

+10 −1
Original line number Diff line number Diff line
@@ -173,13 +173,22 @@ Before jumping into the kernel, the following conditions must be met: 
  the kernel image will be entered must be initialised by software at a

  higher exception level to prevent execution in an UNKNOWN state.



  For systems with a GICv3 interrupt controller:

  For systems with a GICv3 interrupt controller to be used in v3 mode:

  - If EL3 is present:

    ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1.

    ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.

  - If the kernel is entered at EL1:

    ICC.SRE_EL2.Enable (bit 3) must be initialised to 0b1

    ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.

  - The DT or ACPI tables must describe a GICv3 interrupt controller.



  For systems with a GICv3 interrupt controller to be used in

  compatibility (v2) mode:

  - If EL3 is present:

    ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.

  - If the kernel is entered at EL1:

    ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.

  - The DT or ACPI tables must describe a GICv2 interrupt controller.



The requirements described above for CPU mode, caches, MMUs, architected

timers, coherency and system registers apply to all CPUs.  All CPUs must

arch/arm/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -819,6 +819,7 @@ config ARCH_VIRT 
	bool "Dummy Virtual Machine" if ARCH_MULTI_V7

	select ARM_AMBA

	select ARM_GIC

	select ARM_GIC_V3

	select ARM_PSCI

	select HAVE_ARM_ARCH_TIMER

arch/arm/include/asm/arch_gicv3.h

0 → 100644
+188 −0
Original line number Diff line number Diff line 
/*

 * arch/arm/include/asm/arch_gicv3.h

 *

 * Copyright (C) 2015 ARM Ltd.

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __ASM_ARCH_GICV3_H

#define __ASM_ARCH_GICV3_H



#ifndef __ASSEMBLY__



#include <linux/io.h>



#define __ACCESS_CP15(CRn, Op1, CRm, Op2)	p15, Op1, %0, CRn, CRm, Op2

#define __ACCESS_CP15_64(Op1, CRm)		p15, Op1, %Q0, %R0, CRm



#define ICC_EOIR1			__ACCESS_CP15(c12, 0, c12, 1)

#define ICC_DIR				__ACCESS_CP15(c12, 0, c11, 1)

#define ICC_IAR1			__ACCESS_CP15(c12, 0, c12, 0)

#define ICC_SGI1R			__ACCESS_CP15_64(0, c12)

#define ICC_PMR				__ACCESS_CP15(c4, 0, c6, 0)

#define ICC_CTLR			__ACCESS_CP15(c12, 0, c12, 4)

#define ICC_SRE				__ACCESS_CP15(c12, 0, c12, 5)

#define ICC_IGRPEN1			__ACCESS_CP15(c12, 0, c12, 7)



#define ICC_HSRE			__ACCESS_CP15(c12, 4, c9, 5)



#define ICH_VSEIR			__ACCESS_CP15(c12, 4, c9, 4)

#define ICH_HCR				__ACCESS_CP15(c12, 4, c11, 0)

#define ICH_VTR				__ACCESS_CP15(c12, 4, c11, 1)

#define ICH_MISR			__ACCESS_CP15(c12, 4, c11, 2)

#define ICH_EISR			__ACCESS_CP15(c12, 4, c11, 3)

#define ICH_ELSR			__ACCESS_CP15(c12, 4, c11, 5)

#define ICH_VMCR			__ACCESS_CP15(c12, 4, c11, 7)



#define __LR0(x)			__ACCESS_CP15(c12, 4, c12, x)

#define __LR8(x)			__ACCESS_CP15(c12, 4, c13, x)



#define ICH_LR0				__LR0(0)

#define ICH_LR1				__LR0(1)

#define ICH_LR2				__LR0(2)

#define ICH_LR3				__LR0(3)

#define ICH_LR4				__LR0(4)

#define ICH_LR5				__LR0(5)

#define ICH_LR6				__LR0(6)

#define ICH_LR7				__LR0(7)

#define ICH_LR8				__LR8(0)

#define ICH_LR9				__LR8(1)

#define ICH_LR10			__LR8(2)

#define ICH_LR11			__LR8(3)

#define ICH_LR12			__LR8(4)

#define ICH_LR13			__LR8(5)

#define ICH_LR14			__LR8(6)

#define ICH_LR15			__LR8(7)



/* LR top half */

#define __LRC0(x)			__ACCESS_CP15(c12, 4, c14, x)

#define __LRC8(x)			__ACCESS_CP15(c12, 4, c15, x)



#define ICH_LRC0			__LRC0(0)

#define ICH_LRC1			__LRC0(1)

#define ICH_LRC2			__LRC0(2)

#define ICH_LRC3			__LRC0(3)

#define ICH_LRC4			__LRC0(4)

#define ICH_LRC5			__LRC0(5)

#define ICH_LRC6			__LRC0(6)

#define ICH_LRC7			__LRC0(7)

#define ICH_LRC8			__LRC8(0)

#define ICH_LRC9			__LRC8(1)

#define ICH_LRC10			__LRC8(2)

#define ICH_LRC11			__LRC8(3)

#define ICH_LRC12			__LRC8(4)

#define ICH_LRC13			__LRC8(5)

#define ICH_LRC14			__LRC8(6)

#define ICH_LRC15			__LRC8(7)



#define __AP0Rx(x)			__ACCESS_CP15(c12, 4, c8, x)

#define ICH_AP0R0			__AP0Rx(0)

#define ICH_AP0R1			__AP0Rx(1)

#define ICH_AP0R2			__AP0Rx(2)

#define ICH_AP0R3			__AP0Rx(3)



#define __AP1Rx(x)			__ACCESS_CP15(c12, 4, c9, x)

#define ICH_AP1R0			__AP1Rx(0)

#define ICH_AP1R1			__AP1Rx(1)

#define ICH_AP1R2			__AP1Rx(2)

#define ICH_AP1R3			__AP1Rx(3)



/* Low-level accessors */



static inline void gic_write_eoir(u32 irq)

{

	asm volatile("mcr " __stringify(ICC_EOIR1) : : "r" (irq));

	isb();

}



static inline void gic_write_dir(u32 val)

{

	asm volatile("mcr " __stringify(ICC_DIR) : : "r" (val));

	isb();

}



static inline u32 gic_read_iar(void)

{

	u32 irqstat;



	asm volatile("mrc " __stringify(ICC_IAR1) : "=r" (irqstat));

	return irqstat;

}



static inline void gic_write_pmr(u32 val)

{

	asm volatile("mcr " __stringify(ICC_PMR) : : "r" (val));

}



static inline void gic_write_ctlr(u32 val)

{

	asm volatile("mcr " __stringify(ICC_CTLR) : : "r" (val));

	isb();

}



static inline void gic_write_grpen1(u32 val)

{

	asm volatile("mcr " __stringify(ICC_IGRPEN1) : : "r" (val));

	isb();

}



static inline void gic_write_sgi1r(u64 val)

{

	asm volatile("mcrr " __stringify(ICC_SGI1R) : : "r" (val));

}



static inline u32 gic_read_sre(void)

{

	u32 val;



	asm volatile("mrc " __stringify(ICC_SRE) : "=r" (val));

	return val;

}



static inline void gic_write_sre(u32 val)

{

	asm volatile("mcr " __stringify(ICC_SRE) : : "r" (val));

	isb();

}



/*

 * Even in 32bit systems that use LPAE, there is no guarantee that the I/O

 * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't

 * make much sense.

 * Moreover, 64bit I/O emulation is extremely difficult to implement on

 * AArch32, since the syndrome register doesn't provide any information for

 * them.

 * Consequently, the following IO helpers use 32bit accesses.

 *

 * There are only two registers that need 64bit accesses in this driver:

 * - GICD_IROUTERn, contain the affinity values associated to each interrupt.

 *   The upper-word (aff3) will always be 0, so there is no need for a lock.

 * - GICR_TYPER is an ID register and doesn't need atomicity.

 */

static inline void gic_write_irouter(u64 val, volatile void __iomem *addr)

{

	writel_relaxed((u32)val, addr);

	writel_relaxed((u32)(val >> 32), addr + 4);

}



static inline u64 gic_read_typer(const volatile void __iomem *addr)

{

	u64 val;



	val = readl_relaxed(addr);

	val |= (u64)readl_relaxed(addr + 4) << 32;

	return val;

}



#endif /* !__ASSEMBLY__ */

#endif /* !__ASM_ARCH_GICV3_H */

arch/arm64/include/asm/arch_gicv3.h

0 → 100644
+170 −0
Original line number Diff line number Diff line 
/*

 * arch/arm64/include/asm/arch_gicv3.h

 *

 * Copyright (C) 2015 ARM Ltd.

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __ASM_ARCH_GICV3_H

#define __ASM_ARCH_GICV3_H



#include <asm/sysreg.h>



#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)

#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)

#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)

#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)

#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)

#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)

#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)

#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)



#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)



/*

 * System register definitions

 */

#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)

#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)

#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)

#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)

#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)

#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)

#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)



#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)

#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)



#define ICH_LR0_EL2			__LR0_EL2(0)

#define ICH_LR1_EL2			__LR0_EL2(1)

#define ICH_LR2_EL2			__LR0_EL2(2)

#define ICH_LR3_EL2			__LR0_EL2(3)

#define ICH_LR4_EL2			__LR0_EL2(4)

#define ICH_LR5_EL2			__LR0_EL2(5)

#define ICH_LR6_EL2			__LR0_EL2(6)

#define ICH_LR7_EL2			__LR0_EL2(7)

#define ICH_LR8_EL2			__LR8_EL2(0)

#define ICH_LR9_EL2			__LR8_EL2(1)

#define ICH_LR10_EL2			__LR8_EL2(2)

#define ICH_LR11_EL2			__LR8_EL2(3)

#define ICH_LR12_EL2			__LR8_EL2(4)

#define ICH_LR13_EL2			__LR8_EL2(5)

#define ICH_LR14_EL2			__LR8_EL2(6)

#define ICH_LR15_EL2			__LR8_EL2(7)



#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)

#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)

#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)

#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)

#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)



#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)

#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)

#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)

#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)

#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)



#ifndef __ASSEMBLY__



#include <linux/stringify.h>



/*

 * Low-level accessors

 *

 * These system registers are 32 bits, but we make sure that the compiler

 * sets the GP register's most significant bits to 0 with an explicit cast.

 */



static inline void gic_write_eoir(u32 irq)

{

	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" ((u64)irq));

	isb();

}



static inline void gic_write_dir(u32 irq)

{

	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" ((u64)irq));

	isb();

}



static inline u64 gic_read_iar_common(void)

{

	u64 irqstat;



	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	return irqstat;

}



/*

 * Cavium ThunderX erratum 23154

 *

 * The gicv3 of ThunderX requires a modified version for reading the

 * IAR status to ensure data synchronization (access to icc_iar1_el1

 * is not sync'ed before and after).

 */

static inline u64 gic_read_iar_cavium_thunderx(void)

{

	u64 irqstat;



	asm volatile(

		"nop;nop;nop;nop\n\t"

		"nop;nop;nop;nop\n\t"

		"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"

		"nop;nop;nop;nop"

		: "=r" (irqstat));

	mb();



	return irqstat;

}



static inline void gic_write_pmr(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" ((u64)val));

}



static inline void gic_write_ctlr(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" ((u64)val));

	isb();

}



static inline void gic_write_grpen1(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" ((u64)val));

	isb();

}



static inline void gic_write_sgi1r(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

}



static inline u32 gic_read_sre(void)

{

	u64 val;



	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	return val;

}



static inline void gic_write_sre(u32 val)

{

	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" ((u64)val));

	isb();

}



#define gic_read_typer(c)		readq_relaxed(c)

#define gic_write_irouter(v, c)		writeq_relaxed(v, c)



#endif /* __ASSEMBLY__ */

#endif /* __ASM_ARCH_GICV3_H */

arch/arm64/kernel/cpufeature.c

+18 −1
Original line number Diff line number Diff line
@@ -23,6 +23,8 @@ 
#include <asm/cpufeature.h>

#include <asm/processor.h>



#include <linux/irqchip/arm-gic-v3.h>



static bool

feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)

{
@@ -45,11 +47,26 @@ __ID_FEAT_CHK(id_aa64pfr0); 
__ID_FEAT_CHK(id_aa64mmfr1);

__ID_FEAT_CHK(id_aa64isar0);



static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry)

{

	bool has_sre;



	if (!has_id_aa64pfr0_feature(entry))

		return false;



	has_sre = gic_enable_sre();

	if (!has_sre)

		pr_warn_once("%s present but disabled by higher exception level\n",

			     entry->desc);



	return has_sre;

}



static const struct arm64_cpu_capabilities arm64_features[] = {

	{

		.desc = "GIC system register CPU interface",

		.capability = ARM64_HAS_SYSREG_GIC_CPUIF,

		.matches = has_id_aa64pfr0_feature,

		.matches = has_useable_gicv3_cpuif,

		.field_pos = 24,

		.min_field_value = 1,

	},