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Commit fcba34d7 authored by Bao D. Nguyen's avatar Bao D. Nguyen
Browse files

ARM: dts: msm: update embedded UFS device related DT properties on Kona 



This reverts commit a176c21b.
When the UFS ICE is enabled together with the UFS's HW_CTL clocks
being enabled, the UFS transfers fail.
Revert to using the UFS's non-HW_CTL clocks until we understand
the failure better.

Change-Id: Ie974516ad853e21b8f19c833134af07ccdaa6e17
Signed-off-by: default avatarBao D. Nguyen <nguyenb@codeaurora.org>
parent 62a4f0ac

arch/arm64/boot/dts/qcom/kona.dtsi

+8 −6
Original line number Diff line number Diff line
@@ -1867,9 +1867,11 @@ 
		lanes-per-direction = <2>;



		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;

			<&clock_gcc GCC_UFS_1X_CLKREF_EN>,

			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		status = "disabled";

	};
@@ -1896,11 +1898,11 @@ 
			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&clock_gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK>,

			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,

			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
@@ -1910,7 +1912,7 @@ 
			<0 0>,

			<0 0>,

			<37500000 300000000>,

			<37500000 300000000>,

			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,