Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fcb389df authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller
Browse files

tg3: 5785 enhancements 



This patch refines support for the 5785 device.

Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 9c61d6bc

drivers/net/tg3.c

+66 −21
Original line number Diff line number Diff line
@@ -880,10 +880,45 @@ static int tg3_mdio_reset(struct mii_bus *bp) 
static void tg3_mdio_config_5785(struct tg3 *tp)

{

	u32 val;

	struct phy_device *phydev;



	phydev = tp->mdio_bus->phy_map[PHY_ADDR];

	switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {

	case TG3_PHY_ID_BCM50610:

		val = MAC_PHYCFG2_50610_LED_MODES;

		break;

	case TG3_PHY_ID_BCMAC131:

		val = MAC_PHYCFG2_AC131_LED_MODES;

		break;

	case TG3_PHY_ID_RTL8211C:

		val = MAC_PHYCFG2_RTL8211C_LED_MODES;

		break;

	case TG3_PHY_ID_RTL8201E:

		val = MAC_PHYCFG2_RTL8201E_LED_MODES;

		break;

	default:

		return;

	}



	if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {

		tw32(MAC_PHYCFG2, val);



		val = tr32(MAC_PHYCFG1);

		val &= ~MAC_PHYCFG1_RGMII_INT;

		tw32(MAC_PHYCFG1, val);



	if (tp->mdio_bus->phy_map[PHY_ADDR]->interface !=

	    PHY_INTERFACE_MODE_RGMII)

		return;

	}



	if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))

		val |= MAC_PHYCFG2_EMODE_MASK_MASK |

		       MAC_PHYCFG2_FMODE_MASK_MASK |

		       MAC_PHYCFG2_GMODE_MASK_MASK |

		       MAC_PHYCFG2_ACT_MASK_MASK   |

		       MAC_PHYCFG2_QUAL_MASK_MASK |

		       MAC_PHYCFG2_INBAND_ENABLE;



	tw32(MAC_PHYCFG2, val);



	val = tr32(MAC_PHYCFG1) & ~(MAC_PHYCFG1_RGMII_EXT_RX_DEC |

				    MAC_PHYCFG1_RGMII_SND_STAT_EN);
@@ -895,11 +930,6 @@ static void tg3_mdio_config_5785(struct tg3 *tp) 
	}

	tw32(MAC_PHYCFG1, val | MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV);



	val = tr32(MAC_PHYCFG2) & ~(MAC_PHYCFG2_INBAND_ENABLE);

	if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))

		val |= MAC_PHYCFG2_INBAND_ENABLE;

	tw32(MAC_PHYCFG2, val);



	val = tr32(MAC_EXT_RGMII_MODE);

	val &= ~(MAC_RGMII_MODE_RX_INT_B |

		 MAC_RGMII_MODE_RX_QUALITY |
@@ -908,7 +938,7 @@ static void tg3_mdio_config_5785(struct tg3 *tp) 
		 MAC_RGMII_MODE_TX_ENABLE |

		 MAC_RGMII_MODE_TX_LOWPWR |

		 MAC_RGMII_MODE_TX_RESET);

	if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE) {

	if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {

		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)

			val |= MAC_RGMII_MODE_RX_INT_B |

			       MAC_RGMII_MODE_RX_QUALITY |
@@ -1005,14 +1035,17 @@ static int tg3_mdio_init(struct tg3 *tp) 


	switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {

	case TG3_PHY_ID_BCM50610:

		phydev->interface = PHY_INTERFACE_MODE_RGMII;

		if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)

			phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;

		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)

			phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;

		if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)

			phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;

		/* fallthru */

	case TG3_PHY_ID_RTL8211C:

		phydev->interface = PHY_INTERFACE_MODE_RGMII;

		break;

	case TG3_PHY_ID_RTL8201E:

	case TG3_PHY_ID_BCMAC131:

		phydev->interface = PHY_INTERFACE_MODE_MII;

		break;
@@ -1314,6 +1347,15 @@ static void tg3_adjust_link(struct net_device *dev) 
		udelay(40);

	}



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {

		if (phydev->speed == SPEED_10)

			tw32(MAC_MI_STAT,

			     MAC_MI_STAT_10MBPS_MODE |

			     MAC_MI_STAT_LNKSTAT_ATTN_ENAB);

		else

			tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);

	}



	if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)

		tw32(MAC_TX_LENGTHS,

		     ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
@@ -5817,6 +5859,7 @@ static void tg3_restore_pci_state(struct tg3 *tp) 


	pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {

		if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)

			pcie_set_readrq(tp->pdev, 4096);

		else {
@@ -5825,6 +5868,7 @@ static void tg3_restore_pci_state(struct tg3 *tp) 
			pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,

					      tp->pci_lat_timer);

		}

	}



	/* Make sure PCI-X relaxed ordering bit is clear. */

	if (tp->pcix_cap) {
@@ -5980,6 +6024,7 @@ static int tg3_chip_reset(struct tg3 *tp) 
			pci_write_config_dword(tp->pdev, 0xc4,

					       cfg_val | (1 << 15));

		}

		if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)

			/* Set PCIE max payload size and clear error status.  */

			pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);

	}
@@ -7149,8 +7194,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) 
		return err;



	if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {

	    GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {

		/* This value is determined during the probe time DMA

		 * engine test, tg3_test_dma.

		 */
@@ -12156,7 +12200,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
			if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)

				tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;

		}

	}

	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)

		tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;



	/* If we have an AMD 762 or VIA K8T800 chipset, write

	 * reordering to the mailbox registers done by the host

drivers/net/tg3.h

+97 −0
Original line number Diff line number Diff line
@@ -417,6 +417,7 @@ 
#define  MI_COM_DATA_MASK		 0x0000ffff

#define MAC_MI_STAT			0x00000450

#define  MAC_MI_STAT_LNKSTAT_ATTN_ENAB	 0x00000001

#define  MAC_MI_STAT_10MBPS_MODE	 0x00000002

#define MAC_MI_MODE			0x00000454

#define  MAC_MI_MODE_CLK_10MHZ		 0x00000001

#define  MAC_MI_MODE_SHORT_PREAMBLE	 0x00000002
@@ -542,6 +543,100 @@ 
#define  MAC_PHYCFG1_TXC_DRV		 0x20000000

#define MAC_PHYCFG2			0x000005a4

#define  MAC_PHYCFG2_INBAND_ENABLE	 0x00000001

#define  MAC_PHYCFG2_EMODE_MASK_MASK	 0x000001c0

#define  MAC_PHYCFG2_EMODE_MASK_AC131	 0x000000c0

#define  MAC_PHYCFG2_EMODE_MASK_50610	 0x00000100

#define  MAC_PHYCFG2_EMODE_MASK_RT8211	 0x00000000

#define  MAC_PHYCFG2_EMODE_MASK_RT8201	 0x000001c0

#define  MAC_PHYCFG2_EMODE_COMP_MASK	 0x00000e00

#define  MAC_PHYCFG2_EMODE_COMP_AC131	 0x00000600

#define  MAC_PHYCFG2_EMODE_COMP_50610	 0x00000400

#define  MAC_PHYCFG2_EMODE_COMP_RT8211	 0x00000800

#define  MAC_PHYCFG2_EMODE_COMP_RT8201	 0x00000000

#define  MAC_PHYCFG2_FMODE_MASK_MASK	 0x00007000

#define  MAC_PHYCFG2_FMODE_MASK_AC131	 0x00006000

#define  MAC_PHYCFG2_FMODE_MASK_50610	 0x00004000

#define  MAC_PHYCFG2_FMODE_MASK_RT8211	 0x00000000

#define  MAC_PHYCFG2_FMODE_MASK_RT8201	 0x00007000

#define  MAC_PHYCFG2_FMODE_COMP_MASK	 0x00038000

#define  MAC_PHYCFG2_FMODE_COMP_AC131	 0x00030000

#define  MAC_PHYCFG2_FMODE_COMP_50610	 0x00008000

#define  MAC_PHYCFG2_FMODE_COMP_RT8211	 0x00038000

#define  MAC_PHYCFG2_FMODE_COMP_RT8201	 0x00000000

#define  MAC_PHYCFG2_GMODE_MASK_MASK	 0x001c0000

#define  MAC_PHYCFG2_GMODE_MASK_AC131	 0x001c0000

#define  MAC_PHYCFG2_GMODE_MASK_50610	 0x00100000

#define  MAC_PHYCFG2_GMODE_MASK_RT8211	 0x00000000

#define  MAC_PHYCFG2_GMODE_MASK_RT8201	 0x001c0000

#define  MAC_PHYCFG2_GMODE_COMP_MASK	 0x00e00000

#define  MAC_PHYCFG2_GMODE_COMP_AC131	 0x00e00000

#define  MAC_PHYCFG2_GMODE_COMP_50610	 0x00000000

#define  MAC_PHYCFG2_GMODE_COMP_RT8211	 0x00200000

#define  MAC_PHYCFG2_GMODE_COMP_RT8201	 0x00000000

#define  MAC_PHYCFG2_ACT_MASK_MASK	 0x03000000

#define  MAC_PHYCFG2_ACT_MASK_AC131	 0x03000000

#define  MAC_PHYCFG2_ACT_MASK_50610	 0x01000000

#define  MAC_PHYCFG2_ACT_MASK_RT8211	 0x03000000

#define  MAC_PHYCFG2_ACT_MASK_RT8201	 0x01000000

#define  MAC_PHYCFG2_ACT_COMP_MASK	 0x0c000000

#define  MAC_PHYCFG2_ACT_COMP_AC131	 0x00000000

#define  MAC_PHYCFG2_ACT_COMP_50610	 0x00000000

#define  MAC_PHYCFG2_ACT_COMP_RT8211	 0x00000000

#define  MAC_PHYCFG2_ACT_COMP_RT8201	 0x08000000

#define  MAC_PHYCFG2_QUAL_MASK_MASK	 0x30000000

#define  MAC_PHYCFG2_QUAL_MASK_AC131	 0x30000000

#define  MAC_PHYCFG2_QUAL_MASK_50610	 0x30000000

#define  MAC_PHYCFG2_QUAL_MASK_RT8211	 0x30000000

#define  MAC_PHYCFG2_QUAL_MASK_RT8201	 0x30000000

#define  MAC_PHYCFG2_QUAL_COMP_MASK	 0xc0000000

#define  MAC_PHYCFG2_QUAL_COMP_AC131	 0x00000000

#define  MAC_PHYCFG2_QUAL_COMP_50610	 0x00000000

#define  MAC_PHYCFG2_QUAL_COMP_RT8211	 0x00000000

#define  MAC_PHYCFG2_QUAL_COMP_RT8201	 0x00000000

#define MAC_PHYCFG2_50610_LED_MODES \

	(MAC_PHYCFG2_EMODE_MASK_50610 | \

	 MAC_PHYCFG2_EMODE_COMP_50610 | \

	 MAC_PHYCFG2_FMODE_MASK_50610 | \

	 MAC_PHYCFG2_FMODE_COMP_50610 | \

	 MAC_PHYCFG2_GMODE_MASK_50610 | \

	 MAC_PHYCFG2_GMODE_COMP_50610 | \

	 MAC_PHYCFG2_ACT_MASK_50610 | \

	 MAC_PHYCFG2_ACT_COMP_50610 | \

	 MAC_PHYCFG2_QUAL_MASK_50610 | \

	 MAC_PHYCFG2_QUAL_COMP_50610)

#define MAC_PHYCFG2_AC131_LED_MODES \

	(MAC_PHYCFG2_EMODE_MASK_AC131 | \

	 MAC_PHYCFG2_EMODE_COMP_AC131 | \

	 MAC_PHYCFG2_FMODE_MASK_AC131 | \

	 MAC_PHYCFG2_FMODE_COMP_AC131 | \

	 MAC_PHYCFG2_GMODE_MASK_AC131 | \

	 MAC_PHYCFG2_GMODE_COMP_AC131 | \

	 MAC_PHYCFG2_ACT_MASK_AC131 | \

	 MAC_PHYCFG2_ACT_COMP_AC131 | \

	 MAC_PHYCFG2_QUAL_MASK_AC131 | \

	 MAC_PHYCFG2_QUAL_COMP_AC131)

#define MAC_PHYCFG2_RTL8211C_LED_MODES \

	(MAC_PHYCFG2_EMODE_MASK_RT8211 | \

	 MAC_PHYCFG2_EMODE_COMP_RT8211 | \

	 MAC_PHYCFG2_FMODE_MASK_RT8211 | \

	 MAC_PHYCFG2_FMODE_COMP_RT8211 | \

	 MAC_PHYCFG2_GMODE_MASK_RT8211 | \

	 MAC_PHYCFG2_GMODE_COMP_RT8211 | \

	 MAC_PHYCFG2_ACT_MASK_RT8211 | \

	 MAC_PHYCFG2_ACT_COMP_RT8211 | \

	 MAC_PHYCFG2_QUAL_MASK_RT8211 | \

	 MAC_PHYCFG2_QUAL_COMP_RT8211)

#define MAC_PHYCFG2_RTL8201E_LED_MODES \

	(MAC_PHYCFG2_EMODE_MASK_RT8201 | \

	 MAC_PHYCFG2_EMODE_COMP_RT8201 | \

	 MAC_PHYCFG2_FMODE_MASK_RT8201 | \

	 MAC_PHYCFG2_FMODE_COMP_RT8201 | \

	 MAC_PHYCFG2_GMODE_MASK_RT8201 | \

	 MAC_PHYCFG2_GMODE_COMP_RT8201 | \

	 MAC_PHYCFG2_ACT_MASK_RT8201 | \

	 MAC_PHYCFG2_ACT_COMP_RT8201 | \

	 MAC_PHYCFG2_QUAL_MASK_RT8201 | \

	 MAC_PHYCFG2_QUAL_COMP_RT8201)

#define MAC_EXT_RGMII_MODE		0x000005a8

#define  MAC_RGMII_MODE_TX_ENABLE	 0x00000001

#define  MAC_RGMII_MODE_TX_LOWPWR	 0x00000002
@@ -2595,6 +2690,8 @@ struct tg3 { 
#define PHY_REV_BCM5411_X0		0x1 /* Found on Netgear GA302T */

#define TG3_PHY_ID_BCM50610		0x143bd60

#define TG3_PHY_ID_BCMAC131		0x143bc70

#define TG3_PHY_ID_RTL8211C		0x001cc910

#define TG3_PHY_ID_RTL8201E		0x00008200

#define TG3_PHY_OUI_MASK		0xfffffc00

#define TG3_PHY_OUI_1			0x00206000

#define TG3_PHY_OUI_2			0x0143bc00