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Commit fcab86ad authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata 

Pull libata updates from Tejun Heo:

 - ahci grew runtime power management support so that the controller can
   be turned off if no devices are attached.

 - sata_via isn't dead yet.  It got hotplug support and more refined
   workaround for certain WD drives.

 - Misc cleanups.  There's a merge from for-4.5-fixes to avoid confusing
   conflicts in ahci PCI ID table.

* 'for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/libata:
  ata: ahci_xgene: dereferencing uninitialized pointer in probe
  AHCI: Remove obsolete Intel Lewisburg SATA RAID device IDs
  ata: sata_rcar: Use ARCH_RENESAS
  sata_via: Implement hotplug for VT6421
  sata_via: Apply WD workaround only when needed on VT6421
  ahci: Add runtime PM support for the host controller
  ahci: Add functions to manage runtime PM of AHCI ports
  ahci: Convert driver to use modern PM hooks
  ahci: Cache host controller version
  scsi: Drop runtime PM usage count after host is added
  scsi: Set request queue runtime PM status back to active on resume
  block: Add blk_set_runtime_active()
  ata: ahci_mvebu: add support for Armada 3700 variant
  libata: fix unbalanced spin_lock_irqsave/spin_unlock_irq() in ata_scsi_park_show()
  libata: support AHCI on OCTEON platform
parents ef504fa5 8134233e

Documentation/devicetree/bindings/ata/ahci-platform.txt

+1 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ Required properties: 
- compatible        : compatible string, one of:

  - "allwinner,sun4i-a10-ahci"

  - "hisilicon,hisi-ahci"

  - "cavium,octeon-7130-ahci"

  - "ibm,476gtr-ahci"

  - "marvell,armada-380-ahci"

  - "snps,dwc-ahci"

Documentation/devicetree/bindings/mips/cavium/sata-uctl.txt

0 → 100644
+42 −0
Original line number Diff line number Diff line 
* UCTL SATA controller glue



UCTL is the bridge unit between the I/O interconnect (an internal bus)

and the SATA AHCI host controller (UAHC). It performs the following functions:

	- provides interfaces for the applications to access the UAHC AHCI

	  registers on the CN71XX I/O space.

	- provides a bridge for UAHC to fetch AHCI command table entries and data

	  buffers from Level 2 Cache.

	- posts interrupts to the CIU.

	- contains registers that:

		- control the behavior of the UAHC

		- control the clock/reset generation to UAHC

		- control endian swapping for all UAHC registers and DMA accesses



Properties:



- compatible: "cavium,octeon-7130-sata-uctl"



  Compatibility with the cn7130 SOC.



- reg: The base address of the UCTL register bank.



- #address-cells, #size-cells, ranges and dma-ranges must be present and hold

	suitable values to map all child nodes.



Example:



	uctl@118006c000000 {

		compatible = "cavium,octeon-7130-sata-uctl";

		reg = <0x11800 0x6c000000 0x0 0x100>;

		ranges; /* Direct mapping */

		dma-ranges;

		#address-cells = <2>;

		#size-cells = <2>;



		sata: sata@16c0000000000 {

			compatible = "cavium,octeon-7130-ahci";

			reg = <0x16c00 0x00000000 0x0 0x200>;

			interrupt-parent = <&cibsata>;

			interrupts = <2 4>; /* Bit: 2, level */

		};

	};

arch/mips/include/asm/octeon/cvmx.h

+9 −0
Original line number Diff line number Diff line
@@ -275,6 +275,11 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) 
		cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);

}



static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)

{

	cvmx_write_csr((__force uint64_t)csr_addr, val);

}



static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)

{

	cvmx_write64(io_addr, val);
@@ -287,6 +292,10 @@ static inline uint64_t cvmx_read_csr(uint64_t csr_addr) 
	return val;

}



static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)

{

	return cvmx_read_csr((__force uint64_t) csr_addr);

}



static inline void cvmx_send_single(uint64_t data)

{

block/blk-core.c

+24 −0
Original line number Diff line number Diff line
@@ -3529,6 +3529,30 @@ void blk_post_runtime_resume(struct request_queue *q, int err) 
	spin_unlock_irq(q->queue_lock);

}

EXPORT_SYMBOL(blk_post_runtime_resume);



/**

 * blk_set_runtime_active - Force runtime status of the queue to be active

 * @q: the queue of the device

 *

 * If the device is left runtime suspended during system suspend the resume

 * hook typically resumes the device and corrects runtime status

 * accordingly. However, that does not affect the queue runtime PM status

 * which is still "suspended". This prevents processing requests from the

 * queue.

 *

 * This function can be used in driver's resume hook to correct queue

 * runtime PM status and re-enable peeking requests from the queue. It

 * should be called before first request is added to the queue.

 */

void blk_set_runtime_active(struct request_queue *q)

{

	spin_lock_irq(q->queue_lock);

	q->rpm_status = RPM_ACTIVE;

	pm_runtime_mark_last_busy(q->dev);

	pm_request_autosuspend(q->dev);

	spin_unlock_irq(q->queue_lock);

}

EXPORT_SYMBOL(blk_set_runtime_active);

#endif



int __init blk_dev_init(void)

drivers/ata/Kconfig

+10 −1
Original line number Diff line number Diff line
@@ -151,6 +151,15 @@ config AHCI_MVEBU 


	  If unsure, say N.



config AHCI_OCTEON

	tristate "Cavium Octeon Soc Serial ATA"

	depends on SATA_AHCI_PLATFORM && CAVIUM_OCTEON_SOC

	default y

	help

	  This option enables support for Cavium Octeon SoC Serial ATA.



	  If unsure, say N.



config AHCI_SUNXI

	tristate "Allwinner sunxi AHCI SATA support"

	depends on ARCH_SUNXI
@@ -355,7 +364,7 @@ config SATA_PROMISE 


config SATA_RCAR

	tristate "Renesas R-Car SATA support"

	depends on ARCH_SHMOBILE || COMPILE_TEST

	depends on ARCH_RENESAS || COMPILE_TEST

	help

	  This option enables support for Renesas R-Car Serial ATA.