Loading qcom/lito.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -1845,6 +1845,7 @@ "iface_clk", "core_clk_unipro", "core_clk_ice", "core_clk_ice_hw_ctl", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", Loading @@ -1855,6 +1856,7 @@ <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, Loading @@ -1865,6 +1867,7 @@ <0 0>, <37500000 150000000>, <75000000 300000000>, <75000000 300000000>, <0 0>, <0 0>, <0 0>, Loading Loading
qcom/lito.dtsi +3 −0 Original line number Diff line number Diff line Loading @@ -1845,6 +1845,7 @@ "iface_clk", "core_clk_unipro", "core_clk_ice", "core_clk_ice_hw_ctl", "ref_clk", "tx_lane0_sync_clk", "rx_lane0_sync_clk", Loading @@ -1855,6 +1856,7 @@ <&gcc GCC_UFS_PHY_AHB_CLK>, <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, <&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, Loading @@ -1865,6 +1867,7 @@ <0 0>, <37500000 150000000>, <75000000 300000000>, <75000000 300000000>, <0 0>, <0 0>, <0 0>, Loading