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Commit fc4bdb35 authored by Kumar Gala's avatar Kumar Gala
Browse files

powerpc/booke: Move MMUCSR definition into mmu-book3e.h 



The MMUCSR is now defined as part of the Book-3E architecture so we
can move it into mmu-book3e.h and add some of the additional bits
defined by the architecture specs.

Signed-off-by: default avatarKumar Gala <galak@kernel.crashing.org>
parent 8934210c

arch/powerpc/include/asm/mmu-book3e.h

+12 −0
Original line number Diff line number Diff line
@@ -114,6 +114,18 @@ 


#define MAS7_RPN		0xFFFFFFFF



/* Bit definitions for MMUCSR0 */

#define MMUCSR0_TLB1FI	0x00000002	/* TLB1 Flash invalidate */

#define MMUCSR0_TLB0FI	0x00000004	/* TLB0 Flash invalidate */

#define MMUCSR0_TLB2FI	0x00000040	/* TLB2 Flash invalidate */

#define MMUCSR0_TLB3FI	0x00000020	/* TLB3 Flash invalidate */

#define MMUCSR0_TLBFI	(MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \

			 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)

#define MMUCSR0_TLB0PS	0x00000780	/* TLB0 Page Size */

#define MMUCSR0_TLB1PS	0x00007800	/* TLB1 Page Size */

#define MMUCSR0_TLB2PS	0x00078000	/* TLB2 Page Size */

#define MMUCSR0_TLB3PS	0x00780000	/* TLB3 Page Size */



/* TLBnCFG encoding */

#define TLBnCFG_N_ENTRY		0x00000fff	/* number of entries */

#define TLBnCFG_HES		0x00002000	/* HW select supported */

arch/powerpc/include/asm/reg_booke.h

+0 −6
Original line number Diff line number Diff line
@@ -430,12 +430,6 @@ 
#define L2CSR0_L2LOA	0x00000080	/* L2 Cache Lock Overflow Allocate */

#define L2CSR0_L2LO	0x00000020	/* L2 Cache Lock Overflow */



/* Bit definitions for MMUCSR0 */

#define MMUCSR0_TLB1FI	0x00000002	/* TLB1 Flash invalidate */

#define MMUCSR0_TLB0FI	0x00000004	/* TLB0 Flash invalidate */

#define MMUCSR0_TLB2FI	0x00000040	/* TLB2 Flash invalidate */

#define MMUCSR0_TLB3FI	0x00000020	/* TLB3 Flash invalidate */



/* Bit definitions for SGR. */

#define SGR_NORMAL	0		/* Speculative fetching allowed. */

#define SGR_GUARDED	1		/* Speculative fetching disallowed. */

arch/powerpc/mm/tlb_nohash_low.S

+0 −2
Original line number Diff line number Diff line
@@ -124,8 +124,6 @@ _GLOBAL(_tlbil_pid) 
 * to have the larger code path before the _SECTION_ELSE

 */



#define MMUCSR0_TLBFI	(MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \

			 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)

/*

 * Flush MMU TLB on the local processor

 */