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Commit fc31c4e3 authored by Evan Wang's avatar Evan Wang Committed by Lorenzo Pieralisi
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PCI: aardvark: Fix PCIe Max Read Request Size setting 



There is an obvious typo issue in the definition of the PCIe maximum
read request size: a bit shift is directly used as a value, while it
should be used to shift the correct value.

Fixes: 8c39d710 ("PCI: aardvark: Add Aardvark PCI host controller driver")
Cc: <stable@vger.kernel.org>
Signed-off-by: default avatarEvan Wang <xswang@marvell.com>
Reviewed-by: default avatarVictor Gu <xigu@marvell.com>
Reviewed-by: default avatarNadav Haklai <nadavh@marvell.com>
[Thomas: tweak commit log.]
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@bootlin.com>
Signed-off-by: default avatarLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
parent 3430f924

drivers/pci/host/pci-aardvark.c

+3 −1
Original line number Diff line number Diff line
@@ -29,6 +29,7 @@ 
#define     PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT	5

#define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE		(0 << 11)

#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT	12

#define     PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ		0x2

#define PCIE_CORE_LINK_CTRL_STAT_REG				0xd0

#define     PCIE_CORE_LINK_L0S_ENTRY				BIT(0)

#define     PCIE_CORE_LINK_TRAINING				BIT(5)
@@ -295,7 +296,8 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie) 
	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |

		(7 << PCIE_CORE_DEV_CTRL_STATS_MAX_PAYLOAD_SZ_SHIFT) |

		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE |

		PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT;

		(PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SZ <<

		 PCIE_CORE_DEV_CTRL_STATS_MAX_RD_REQ_SIZE_SHIFT);

	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);



	/* Program PCIe Control 2 to disable strict ordering */