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Commit fbf68229 authored by LABBE Corentin's avatar LABBE Corentin Committed by David S. Miller
Browse files

net: stmmac: unify registers dumps methods 



The stmmac driver have two methods for registers dumps: via ethtool and
at init (if NETIF_MSG_HW is enabled).

It is better to keep only one method, ethtool, since the other was ugly.

This patch convert all dump_regs() function from "printing regs" to
"fill the reg_space used by ethtool".

Signed-off-by: default avatarCorentin Labbe <clabbe.montjoie@gmail.com>
Acked-by: default avatarGiuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 77cc7aee

drivers/net/ethernet/stmicro/stmmac/common.h

+2 −2
Original line number Diff line number Diff line
@@ -416,7 +416,7 @@ struct stmmac_dma_ops { 
	/* Configure the AXI Bus Mode Register */

	void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);

	/* Dump DMA registers */

	void (*dump_regs) (void __iomem *ioaddr);

	void (*dump_regs)(void __iomem *ioaddr, u32 *reg_space);

	/* Set tx/rx threshold in the csr6 register

	 * An invalid value enables the store-and-forward mode */

	void (*dma_mode)(void __iomem *ioaddr, int txmode, int rxmode,
@@ -456,7 +456,7 @@ struct stmmac_ops { 
	/* Enable RX Queues */

	void (*rx_queue_enable)(struct mac_device_info *hw, u32 queue);

	/* Dump MAC registers */

	void (*dump_regs)(struct mac_device_info *hw);

	void (*dump_regs)(struct mac_device_info *hw, u32 *reg_space);

	/* Handle extra events on specific interrupts hw dependent */

	int (*host_irq_status)(struct mac_device_info *hw,

			       struct stmmac_extra_stats *x);

drivers/net/ethernet/stmicro/stmmac/dwmac1000_core.c

+3 −7
Original line number Diff line number Diff line
@@ -92,17 +92,13 @@ static int dwmac1000_rx_ipc_enable(struct mac_device_info *hw) 
	return !!(value & GMAC_CONTROL_IPC);

}



static void dwmac1000_dump_regs(struct mac_device_info *hw)

static void dwmac1000_dump_regs(struct mac_device_info *hw, u32 *reg_space)

{

	void __iomem *ioaddr = hw->pcsr;

	int i;

	pr_info("\tDWMAC1000 regs (base addr = 0x%p)\n", ioaddr);



	for (i = 0; i < 55; i++) {

		int offset = i * 4;

		pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,

			offset, readl(ioaddr + offset));

	}

	for (i = 0; i < 55; i++)

		reg_space[i] = readl(ioaddr + i * 4);

}



static void dwmac1000_set_umac_addr(struct mac_device_info *hw,

drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

+6 −10
Original line number Diff line number Diff line
@@ -201,18 +201,14 @@ static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode, 
	writel(csr6, ioaddr + DMA_CONTROL);

}



static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)

static void dwmac1000_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)

{

	int i;

	pr_info(" DMA registers\n");

	for (i = 0; i < 22; i++) {

		if ((i < 9) || (i > 17)) {

			int offset = i * 4;

			pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,

			       (DMA_BUS_MODE + offset),

			       readl(ioaddr + DMA_BUS_MODE + offset));

		}

	}



	for (i = 0; i < 22; i++)

		if ((i < 9) || (i > 17))

			reg_space[DMA_BUS_MODE / 4 + i] =

				readl(ioaddr + DMA_BUS_MODE + i * 4);

}



static void dwmac1000_get_hw_feature(void __iomem *ioaddr,

drivers/net/ethernet/stmicro/stmmac/dwmac100_core.c

+10 −20
Original line number Diff line number Diff line
@@ -40,28 +40,18 @@ static void dwmac100_core_init(struct mac_device_info *hw, int mtu) 
#endif

}



static void dwmac100_dump_mac_regs(struct mac_device_info *hw)

static void dwmac100_dump_mac_regs(struct mac_device_info *hw, u32 *reg_space)

{

	void __iomem *ioaddr = hw->pcsr;

	pr_info("\t----------------------------------------------\n"

		"\t  DWMAC 100 CSR (base addr = 0x%p)\n"

		"\t----------------------------------------------\n", ioaddr);

	pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,

		readl(ioaddr + MAC_CONTROL));

	pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,

		readl(ioaddr + MAC_ADDR_HIGH));

	pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,

		readl(ioaddr + MAC_ADDR_LOW));

	pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",

		MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));

	pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",

		MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));

	pr_info("\tflow control (offset 0x%x): 0x%08x\n",

		MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));

	pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,

		readl(ioaddr + MAC_VLAN1));

	pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,

		readl(ioaddr + MAC_VLAN2));



	reg_space[MAC_CONTROL / 4] = readl(ioaddr + MAC_CONTROL);

	reg_space[MAC_ADDR_HIGH / 4] = readl(ioaddr + MAC_ADDR_HIGH);

	reg_space[MAC_ADDR_LOW / 4] = readl(ioaddr + MAC_ADDR_LOW);

	reg_space[MAC_HASH_HIGH / 4] = readl(ioaddr + MAC_HASH_HIGH);

	reg_space[MAC_HASH_LOW / 4] = readl(ioaddr + MAC_HASH_LOW);

	reg_space[MAC_FLOW_CTRL / 4] = readl(ioaddr + MAC_FLOW_CTRL);

	reg_space[MAC_VLAN1 / 4] = readl(ioaddr + MAC_VLAN1);

	reg_space[MAC_VLAN2 / 4] = readl(ioaddr + MAC_VLAN2);

}



static int dwmac100_rx_ipc_enable(struct mac_device_info *hw)

drivers/net/ethernet/stmicro/stmmac/dwmac100_dma.c

+7 −8
Original line number Diff line number Diff line
@@ -66,19 +66,18 @@ static void dwmac100_dma_operation_mode(void __iomem *ioaddr, int txmode, 
	writel(csr6, ioaddr + DMA_CONTROL);

}



static void dwmac100_dump_dma_regs(void __iomem *ioaddr)

static void dwmac100_dump_dma_regs(void __iomem *ioaddr, u32 *reg_space)

{

	int i;



	pr_debug("DWMAC 100 DMA CSR\n");

	for (i = 0; i < 9; i++)

		pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,

			 (DMA_BUS_MODE + i * 4),

			 readl(ioaddr + DMA_BUS_MODE + i * 4));

		reg_space[DMA_BUS_MODE / 4 + i] =

			readl(ioaddr + DMA_BUS_MODE + i * 4);



	pr_debug("\tCSR20 (0x%x): 0x%08x, CSR21 (0x%x): 0x%08x\n",

		 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR),

		 DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));

	reg_space[DMA_CUR_TX_BUF_ADDR / 4] =

		readl(ioaddr + DMA_CUR_TX_BUF_ADDR);

	reg_space[DMA_CUR_RX_BUF_ADDR / 4] =

		readl(ioaddr + DMA_CUR_RX_BUF_ADDR);

}



/* DMA controller has two counters to track the number of the missed frames. */