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Commit fab38333 authored by Thinh Nguyen's avatar Thinh Nguyen Committed by Felipe Balbi
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usb: dwc3: Add SoftReset PHY synchonization delay 



From DWC_usb31 programming guide section 1.3.2, once DWC3_DCTL_CSFTRST
bit is cleared, we must wait at least 50ms before accessing the PHY
domain (synchronization delay).

Signed-off-by: default avatarThinh Nguyen <thinhn@synopsys.com>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent cabdf83d

drivers/usb/dwc3/core.c

+12 −1
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) 
	do {

		reg = dwc3_readl(dwc->regs, DWC3_DCTL);

		if (!(reg & DWC3_DCTL_CSFTRST))

			return 0;

			goto done;



		udelay(1);

	} while (--retries);
@@ -253,6 +253,17 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) 
	phy_exit(dwc->usb2_generic_phy);



	return -ETIMEDOUT;



done:

	/*

	 * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,

	 * we must wait at least 50ms before accessing the PHY domain

	 * (synchronization delay). DWC_usb31 programming guide section 1.3.2.

	 */

	if (dwc3_is_usb31(dwc))

		msleep(50);



	return 0;

}



/*