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Commit faa865f1 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-v4.15-samsung' of... 

Merge tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-next

Pull Samsung clk driver updates from Sylwester Nawrocki:

Overall clk/samsung clean up and fixes. Removed remaining unused code
after removal of exynos4212 SoC support; dropped internal data structure
fields and related code for registering clkdev lookup entry for each
possible clock object, clkdev aliases could still be defined if needed
in a separate table; other minor fixes of the clock tree definitions.

* tag 'clk-v4.15-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
  clk: samsung: Remove obsolete clkdev alias support
  clk: samsung: Add explicit MPLL, EPLL clkdev aliases in S3C2443 driver
  clk: samsung: Rework clkdev alias handling in S3C2443 driver
  clk: samsung: Rework clkdev alias handling in Exynos5440 driver
  clk: samsung: Drop useless alias in Exynos5420 clk driver
  clk: samsung: Remove clkdev alias support in Exynos5250 clk driver
  clk: samsung: Remove double assignment of CLK_ARM_CLK in Exynos4 driver
  clk: samsung: Remove clkdev alias support in Exynos4 clk driver
  clk: samsung: Remove support for obsolete Exynos4212 CPU clock
  clk: samsung: Remove support for Exynos4212 SoCs in Exynos CLKOUT driver
  clk: samsung: Properly propagate flags in __PLL macro
  clk: samsung: Fix m2m scaler clock on Exynos542x
  clk: samsung: Delete a memory allocation error message in clk-cpu.c
parents f09a6b86 a4f21e9c

drivers/clk/samsung/clk-cpu.c

+0 −2
Original line number Diff line number Diff line
@@ -457,8 +457,6 @@ int __init exynos_register_cpu_clock(struct samsung_clk_provider *ctx, 


	cpuclk->cfg = kmemdup(cfg, sizeof(*cfg) * num_cfgs, GFP_KERNEL);

	if (!cpuclk->cfg) {

		pr_err("%s: could not allocate memory for cpuclk data\n",

				__func__);

		ret = -ENOMEM;

		goto unregister_clk_nb;

	}

drivers/clk/samsung/clk-exynos-clkout.c

+0 −2
Original line number Diff line number Diff line
@@ -144,8 +144,6 @@ static void __init exynos4_clkout_init(struct device_node *node) 
}

CLK_OF_DECLARE_DRIVER(exynos4210_clkout, "samsung,exynos4210-pmu",

		exynos4_clkout_init);

CLK_OF_DECLARE_DRIVER(exynos4212_clkout, "samsung,exynos4212-pmu",

		exynos4_clkout_init);

CLK_OF_DECLARE_DRIVER(exynos4412_clkout, "samsung,exynos4412-pmu",

		exynos4_clkout_init);

CLK_OF_DECLARE_DRIVER(exynos3250_clkout, "samsung,exynos3250-pmu",

drivers/clk/samsung/clk-exynos4.c

+15 −67
Original line number Diff line number Diff line
@@ -550,9 +550,8 @@ static const struct samsung_fixed_factor_clock exynos4x12_fixed_factor_clks[] __ 


/* list of mux clocks supported in all exynos4 soc's */

static const struct samsung_mux_clock exynos4_mux_clks[] __initconst = {

	MUX_FA(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,

			CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0,

			"mout_apll"),

	MUX_F(CLK_MOUT_APLL, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,

			CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),

	MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_TV, 0, 1),

	MUX(0, "mout_mfc1", sclk_evpll_p, SRC_MFC, 4, 1),

	MUX(0, "mout_mfc", mout_mfc_p, SRC_MFC, 8, 1),
@@ -737,7 +736,7 @@ static const struct samsung_div_clock exynos4_div_clks[] __initconst = { 
	DIV(0, "div_periph", "div_core2", DIV_CPU0, 12, 3),

	DIV(0, "div_atb", "mout_core", DIV_CPU0, 16, 3),

	DIV(0, "div_pclk_dbg", "div_atb", DIV_CPU0, 20, 3),

	DIV(CLK_ARM_CLK, "div_core2", "div_core", DIV_CPU0, 28, 3),

	DIV(0, "div_core2", "div_core", DIV_CPU0, 28, 3),

	DIV(0, "div_copy", "mout_hpm", DIV_CPU1, 0, 3),

	DIV(0, "div_hpm", "div_copy", DIV_CPU1, 4, 3),

	DIV(0, "div_clkout_cpu", "mout_clkout_cpu", CLKOUT_CMU_CPU, 8, 6),
@@ -853,11 +852,6 @@ static const struct samsung_div_clock exynos4x12_div_clks[] __initconst = { 


/* list of gate clocks supported in all exynos4 soc's */

static const struct samsung_gate_clock exynos4_gate_clks[] __initconst = {

	/*

	 * After all Exynos4 based platforms are migrated to use device tree,

	 * the device name and clock alias names specified below for some

	 * of the clocks can be removed.

	 */

	GATE(CLK_PPMULEFT, "ppmuleft", "aclk200", GATE_IP_LEFTBUS, 1, 0, 0),

	GATE(CLK_PPMURIGHT, "ppmuright", "aclk200", GATE_IP_RIGHTBUS, 1, 0, 0),

	GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi", SRC_MASK_TV, 0, 0, 0),
@@ -1205,20 +1199,6 @@ static const struct samsung_gate_clock exynos4x12_gate_clks[] __initconst = { 
		0),

};



static const struct samsung_clock_alias exynos4_aliases[] __initconst = {

	ALIAS(CLK_MOUT_CORE, NULL, "moutcore"),

	ALIAS(CLK_ARM_CLK, NULL, "armclk"),

	ALIAS(CLK_SCLK_APLL, NULL, "mout_apll"),

};



static const struct samsung_clock_alias exynos4210_aliases[] __initconst = {

	ALIAS(CLK_SCLK_MPLL, NULL, "mout_mpll"),

};



static const struct samsung_clock_alias exynos4x12_aliases[] __initconst = {

	ALIAS(CLK_MOUT_MPLL_USER_C, NULL, "mout_mpll"),

};



/*

 * The parent of the fin_pll clock is selected by the XOM[0] bit. This bit

 * resides in chipid register space, outside of the clock controller memory
@@ -1355,14 +1335,14 @@ static const struct samsung_pll_rate_table exynos4x12_vpll_rates[] __initconst = 
};



static struct samsung_pll_clock exynos4210_plls[nr_plls] __initdata = {

	[apll] = PLL_A(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",

		APLL_LOCK, APLL_CON0, "fout_apll", NULL),

	[mpll] = PLL_A(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",

		E4210_MPLL_LOCK, E4210_MPLL_CON0, "fout_mpll", NULL),

	[epll] = PLL_A(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",

		EPLL_LOCK, EPLL_CON0, "fout_epll", NULL),

	[vpll] = PLL_A(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",

		VPLL_LOCK, VPLL_CON0, "fout_vpll", NULL),

	[apll] = PLL(pll_4508, CLK_FOUT_APLL, "fout_apll", "fin_pll",

		APLL_LOCK, APLL_CON0, NULL),

	[mpll] = PLL(pll_4508, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",

		E4210_MPLL_LOCK, E4210_MPLL_CON0, NULL),

	[epll] = PLL(pll_4600, CLK_FOUT_EPLL, "fout_epll", "fin_pll",

		EPLL_LOCK, EPLL_CON0, NULL),

	[vpll] = PLL(pll_4650c, CLK_FOUT_VPLL, "fout_vpll", "mout_vpllsrc",

		VPLL_LOCK, VPLL_CON0, NULL),

};



static struct samsung_pll_clock exynos4x12_plls[nr_plls] __initdata = {
@@ -1416,24 +1396,6 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { 
	{  0 },

};



static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {

	{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },

	{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },

	{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },

	{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },

	{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },

	{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },

	{  900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },

	{  800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },

	{  700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },

	{  200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },

	{  0 },

};



#define E4412_CPU_DIV1(cores, hpm, copy)				\

		(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
@@ -1527,8 +1489,6 @@ static void __init exynos4_clk_init(struct device_node *np, 
			ARRAY_SIZE(exynos4210_div_clks));

		samsung_clk_register_gate(ctx, exynos4210_gate_clks,

			ARRAY_SIZE(exynos4210_gate_clks));

		samsung_clk_register_alias(ctx, exynos4210_aliases,

			ARRAY_SIZE(exynos4210_aliases));

		samsung_clk_register_fixed_factor(ctx,

			exynos4210_fixed_factor_clks,

			ARRAY_SIZE(exynos4210_fixed_factor_clks));
@@ -1543,26 +1503,14 @@ static void __init exynos4_clk_init(struct device_node *np, 
			ARRAY_SIZE(exynos4x12_div_clks));

		samsung_clk_register_gate(ctx, exynos4x12_gate_clks,

			ARRAY_SIZE(exynos4x12_gate_clks));

		samsung_clk_register_alias(ctx, exynos4x12_aliases,

			ARRAY_SIZE(exynos4x12_aliases));

		samsung_clk_register_fixed_factor(ctx,

			exynos4x12_fixed_factor_clks,

			ARRAY_SIZE(exynos4x12_fixed_factor_clks));

		if (of_machine_is_compatible("samsung,exynos4412")) {

		exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

			mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,

			e4412_armclk_d, ARRAY_SIZE(e4412_armclk_d),

			CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);

		} else {

			exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",

				mout_core_p4x12[0], mout_core_p4x12[1], 0x14200,

				e4212_armclk_d, ARRAY_SIZE(e4212_armclk_d),

				CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1);

	}

	}



	samsung_clk_register_alias(ctx, exynos4_aliases,

			ARRAY_SIZE(exynos4_aliases));



	if (soc == EXYNOS4X12)

		exynos4x12_core_down_clock();

drivers/clk/samsung/clk-exynos5250.c

+9 −9
Original line number Diff line number Diff line
@@ -293,14 +293,14 @@ static const struct samsung_mux_clock exynos5250_mux_clks[] __initconst = { 
	/*

	 * CMU_CPU

	 */

	MUX_FA(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,

					CLK_SET_RATE_PARENT, 0, "mout_apll"),

	MUX_A(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1, "mout_cpu"),

	MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,

					CLK_SET_RATE_PARENT, 0),

	MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),



	/*

	 * CMU_CORE

	 */

	MUX_A(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1, "mout_mpll"),

	MUX(0, "mout_mpll", mout_mpll_p, SRC_CORE1, 8, 1),



	/*

	 * CMU_TOP
@@ -391,7 +391,7 @@ static const struct samsung_div_clock exynos5250_div_clks[] __initconst = { 
	 */

	DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),

	DIV(0, "div_apll", "mout_apll", DIV_CPU0, 24, 3),

	DIV_A(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3, "armclk"),

	DIV(0, "div_arm2", "div_arm", DIV_CPU0, 28, 3),



	/*

	 * CMU_TOP
@@ -743,10 +743,10 @@ static const struct samsung_pll_rate_table apll_24mhz_tbl[] __initconst = { 
};



static struct samsung_pll_clock exynos5250_plls[nr_plls] __initdata = {

	[apll] = PLL_A(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll",

		APLL_LOCK, APLL_CON0, "fout_apll", NULL),

	[mpll] = PLL_A(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll",

		MPLL_LOCK, MPLL_CON0, "fout_mpll", NULL),

	[apll] = PLL(pll_35xx, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,

		APLL_CON0, NULL),

	[mpll] = PLL(pll_35xx, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,

		MPLL_CON0, NULL),

	[bpll] = PLL(pll_35xx, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,

		BPLL_CON0, NULL),

	[gpll] = PLL(pll_35xx, CLK_FOUT_GPLL, "fout_gpll", "fin_pll", GPLL_LOCK,

drivers/clk/samsung/clk-exynos5420.c

+2 −3
Original line number Diff line number Diff line
@@ -600,8 +600,7 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = { 
				TOP_SPARE2, 4, 1),



	MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),

	MUX_A(0, "mout_aclk400_mscl", mout_group1_p,

				SRC_TOP0, 4, 2, "aclk400_mscl"),

	MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),

	MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),

	MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
@@ -998,7 +997,7 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { 
	GATE(0, "aclk400_isp", "mout_user_aclk400_isp",

			GATE_BUS_TOP, 16, 0, 0),

	GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",

			GATE_BUS_TOP, 17, 0, 0),

			GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),

	GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",

			GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),

	GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",