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Commit fa8e6d58 authored by Jagdish Gediya's avatar Jagdish Gediya Committed by Boris Brezillon
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mtd: nand: fsl_ifc: Fix nand waitfunc return value 



As per the IFC hardware manual, Most significant 2 bytes in
nand_fsr register are the outcome of NAND READ STATUS command.

So status value need to be shifted and aligned as per the nand
framework requirement.

Fixes: 82771882 ("NAND Machine support for Integrated Flash Controller")
Cc: stable@vger.kernel.org # v3.18+
Signed-off-by: default avatarJagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: default avatarPrabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@bootlin.com>
parent 6de56493

drivers/mtd/nand/fsl_ifc_nand.c

+3 −2
Original line number Diff line number Diff line
@@ -626,6 +626,7 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) 
	struct fsl_ifc_ctrl *ctrl = priv->ctrl;

	struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;

	u32 nand_fsr;

	int status;



	/* Use READ_STATUS command, but wait for the device to be ready */

	ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
@@ -640,12 +641,12 @@ static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip) 
	fsl_ifc_run_command(mtd);



	nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);



	status = nand_fsr >> 24;

	/*

	 * The chip always seems to report that it is

	 * write-protected, even when it is not.

	 */

	return nand_fsr | NAND_STATUS_WP;

	return status | NAND_STATUS_WP;

}



/*