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Commit fa50e452 authored by Asha Magadi Venkateshamurthy's avatar Asha Magadi Venkateshamurthy Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: add default cachemiss-ev for ddr memlat on sdm660 

cachemiss event if not configured, driver will not set to default
value resulting in probe error. So setting cachemiss-ev to default
0x17 which is L2DM_EV.

Change-Id: Ic90cbbf93fbf9073874aa39aa5869cef6e45160f
parent f684f506

qcom/sdm660.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -1105,6 +1105,7 @@ 
			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;

			qcom,target-dev = <&cpu0_cpu_ddr_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table =

				< 902400 MHZ_TO_MBPS(200, 4) >,

				< 1401600 MHZ_TO_MBPS(547, 4) >,
@@ -1130,6 +1131,7 @@ 
			compatible = "qcom,arm-memlat-mon";

			qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;

			qcom,target-dev = <&cpu4_cpu_ddr_lat>;

			qcom,cachemiss-ev = <0x17>;

			qcom,core-dev-table =

				< 1113600 MHZ_TO_MBPS(200, 4) >,

				< 1401600 MHZ_TO_MBPS(1017, 4) >,