Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit fa14fa5f authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "msm: ipa: Update MHI UL resource groups"

parents e6c59589 f5f9f76e

drivers/platform/msm/ipa/ipa_v3/ipa_utils.c

+5 −5
Original line number Original line Diff line number Diff line
@@ -2622,32 +2622,32 @@ static const struct ipa_ep_configuration ipa3_ep_mapping 
			{ 31, 31, 8, 8, IPA_EE_AP } },

			{ 31, 31, 8, 8, IPA_EE_AP } },

	/* MHI PRIME PIPES - Client producer / IPA Consumer pipes */

	/* MHI PRIME PIPES - Client producer / IPA Consumer pipes */

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_DPL_PROD] = {

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_DPL_PROD] = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			true,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			QMB_MASTER_SELECT_DDR,

			{3, 2, 8, 16, IPA_EE_AP } },

			{3, 2, 8, 16, IPA_EE_AP } },

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_TETH_PROD] = {

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_TETH_PROD] = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			true,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			IPA_DPS_HPS_SEQ_TYPE_2ND_PKT_PROCESS_PASS_NO_DEC_UCP,

			QMB_MASTER_SELECT_DDR,

			QMB_MASTER_SELECT_DDR,

			{ 2, 7, 8, 16, IPA_EE_AP } },

			{ 2, 7, 8, 16, IPA_EE_AP } },

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_RMNET_PROD] = {

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_RMNET_PROD] = {

			true, IPA_v4_5_MHI_GROUP_DDR,

			true, IPA_v4_5_GROUP_UL_DL,

			true,

			true,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			IPA_DPS_HPS_SEQ_TYPE_DMA_ONLY,

			QMB_MASTER_SELECT_DDR,

			QMB_MASTER_SELECT_DDR,

			{ 4, 11, 16, 32, IPA_EE_AP } },

			{ 4, 11, 16, 32, IPA_EE_AP } },

	/* MHI PRIME PIPES - Client Consumer / IPA Producer pipes */

	/* MHI PRIME PIPES - Client Consumer / IPA Producer pipes */

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_TETH_CONS] = {

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_TETH_CONS] = {

			true, IPA_v4_5_MHI_GROUP_PCIE,

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			QMB_MASTER_SELECT_DDR,

			{ 28, 6, 9, 9, IPA_EE_AP } },

			{ 28, 6, 9, 9, IPA_EE_AP } },

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_RMNET_CONS] = {

	[IPA_4_5_APQ][IPA_CLIENT_MHI_PRIME_RMNET_CONS] = {

			true, IPA_v4_5_MHI_GROUP_PCIE,

			true, IPA_v4_5_GROUP_UL_DL,

			false,

			false,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			IPA_DPS_HPS_SEQ_TYPE_INVALID,

			QMB_MASTER_SELECT_DDR,

			QMB_MASTER_SELECT_DDR,