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Commit f9400afb authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/mmu/gp100,gp10b: implement new vmm backend 



Adds support for:
- 64KiB/2MiB big page sizes (128KiB not supported by HW with new PT layout).
- System-memory PTs.
- LPTE "invalid" state.
- (Tegra) Use of video memory aperture.
- Sparse PDEs/PTEs.
- Additional blocklinear kinds.
- 49-bit address-space.

GP100 supports an entirely new 5-level page table layout that provides
an expanded 49-bit address-space.  It also supports the layout present
on previous generations, which we've been making do with until now.

This commit implements support for the new layout, and enables it by
default.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e12cf6ad

drivers/gpu/drm/nouveau/include/nvif/ifc00d.h

+13 −0
Original line number Diff line number Diff line
@@ -5,4 +5,17 @@ 
struct gp100_vmm_vn {

	/* nvif_vmm_vX ... */

};



struct gp100_vmm_map_vn {

	/* nvif_vmm_map_vX ... */

};



struct gp100_vmm_map_v0 {

	/* nvif_vmm_map_vX ... */

	__u8  version;

	__u8  vol;

	__u8  ro;

	__u8  priv;

	__u8  kind;

};

#endif

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.c

+0 −123
Original line number Diff line number Diff line
@@ -23,10 +23,6 @@ 
 */

#include "vmm.h"



#include <core/gpuobj.h>

#include <subdev/fb.h>

#include <subdev/timer.h>



#include <nvif/class.h>



/* Map from compressed to corresponding uncompressed storage type.
@@ -75,125 +71,6 @@ gf100_mmu_kind(struct nvkm_mmu *mmu, int *count) 
	return gf100_pte_storage_type_map;

}



void

gf100_vm_map_pgt(struct nvkm_vmm *vmm, u32 index, struct nvkm_memory *pgt[2])

{

	struct nvkm_memory *pgd = vmm->pd->pt[0]->memory;

	u32 pde[2] = { 0, 0 };



	if (pgt[0])

		pde[1] = 0x00000001 | (nvkm_memory_addr(pgt[0]) >> 8);

	if (pgt[1])

		pde[0] = 0x00000001 | (nvkm_memory_addr(pgt[1]) >> 8);



	nvkm_kmap(pgd);

	nvkm_wo32(pgd, (index * 8) + 0, pde[0]);

	nvkm_wo32(pgd, (index * 8) + 4, pde[1]);

	nvkm_done(pgd);

}



static inline u64

gf100_vm_addr(struct nvkm_vma *vma, u64 phys, u32 memtype, u32 target)

{

	phys >>= 8;



	phys |= 0x00000001; /* present */

	if (vma->access & NV_MEM_ACCESS_SYS)

		phys |= 0x00000002;



	phys |= ((u64)target  << 32);

	phys |= ((u64)memtype << 36);

	return phys;

}



void

gf100_vm_map(struct nvkm_vma *vma, struct nvkm_memory *pgt,

	     struct nvkm_mem *mem, u32 pte, u32 cnt, u64 phys, u64 delta)

{

	u64 next = 1 << (vma->node->type - 8);



	phys  = gf100_vm_addr(vma, phys, mem->memtype, 0);

	pte <<= 3;



	if (mem->tag) {

		u32 tag = mem->tag->offset + (delta >> 17);

		phys |= (u64)tag << (32 + 12);

		next |= (u64)1   << (32 + 12);

	}



	nvkm_kmap(pgt);

	while (cnt--) {

		nvkm_wo32(pgt, pte + 0, lower_32_bits(phys));

		nvkm_wo32(pgt, pte + 4, upper_32_bits(phys));

		phys += next;

		pte  += 8;

	}

	nvkm_done(pgt);

}



void

gf100_vm_map_sg(struct nvkm_vma *vma, struct nvkm_memory *pgt,

		struct nvkm_mem *mem, u32 pte, u32 cnt, dma_addr_t *list)

{

	u32 target = (vma->access & NV_MEM_ACCESS_NOSNOOP) ? 7 : 5;

	/* compressed storage types are invalid for system memory */

	u32 memtype = gf100_pte_storage_type_map[mem->memtype & 0xff];



	nvkm_kmap(pgt);

	pte <<= 3;

	while (cnt--) {

		u64 phys = gf100_vm_addr(vma, *list++, memtype, target);

		nvkm_wo32(pgt, pte + 0, lower_32_bits(phys));

		nvkm_wo32(pgt, pte + 4, upper_32_bits(phys));

		pte += 8;

	}

	nvkm_done(pgt);

}



void

gf100_vm_unmap(struct nvkm_vma *vma, struct nvkm_memory *pgt, u32 pte, u32 cnt)

{

	nvkm_kmap(pgt);

	pte <<= 3;

	while (cnt--) {

		nvkm_wo32(pgt, pte + 0, 0x00000000);

		nvkm_wo32(pgt, pte + 4, 0x00000000);

		pte += 8;

	}

	nvkm_done(pgt);

}



void

gf100_vm_flush(struct nvkm_vm *vm)

{

	struct nvkm_mmu *mmu = vm->mmu;

	struct nvkm_device *device = mmu->subdev.device;

	u32 type;



	type = 0x00000001; /* PAGE_ALL */

	if (atomic_read(&vm->engref[NVKM_SUBDEV_BAR]))

		type |= 0x00000004; /* HUB_ONLY */



	mutex_lock(&mmu->subdev.mutex);

	/* looks like maybe a "free flush slots" counter, the

	 * faster you write to 0x100cbc to more it decreases

	 */

	nvkm_msec(device, 2000,

		if (nvkm_rd32(device, 0x100c80) & 0x00ff0000)

			break;

	);



	nvkm_wr32(device, 0x100cb8, vm->pd->pt[0]->addr >> 8);

	nvkm_wr32(device, 0x100cbc, 0x80000000 | type);



	/* wait for flush to be queued? */

	nvkm_msec(device, 2000,

		if (nvkm_rd32(device, 0x100c80) & 0x00008000)

			break;

	);

	mutex_unlock(&mmu->subdev.mutex);

}



static const struct nvkm_mmu_func

gf100_mmu = {

	.limit = (1ULL << 40),

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.c

+2 −1
Original line number Diff line number Diff line
@@ -31,12 +31,13 @@ gp100_mmu = { 
	.dma_bits = 47,

	.lpg_shift = 16,

	.vmm = {{ -1, -1, NVIF_CLASS_VMM_GP100}, gp100_vmm_new },

	.kind = gm200_mmu_kind,

};



int

gp100_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)

{

	if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", false))

	if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true))

		return gm200_mmu_new(device, index, pmmu);

	return nvkm_mmu_new_(&gp100_mmu, device, index, pmmu);

}

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.

0 → 100644
+0 −0

Empty file added.

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.c

+2 −1
Original line number Diff line number Diff line
@@ -31,12 +31,13 @@ gp10b_mmu = { 
	.dma_bits = 47,

	.lpg_shift = 16,

	.vmm = {{ -1, -1, NVIF_CLASS_VMM_GP100}, gp10b_vmm_new },

	.kind = gm200_mmu_kind,

};



int

gp10b_mmu_new(struct nvkm_device *device, int index, struct nvkm_mmu **pmmu)

{

	if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", false))

	if (!nvkm_boolopt(device->cfgopt, "GP100MmuLayout", true))

		return gm20b_mmu_new(device, index, pmmu);

	return nvkm_mmu_new_(&gp10b_mmu, device, index, pmmu);

}