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Commit f915084e authored by Gaurav K Singh's avatar Gaurav K Singh Committed by Daniel Vetter
Browse files

drm/i915: Changes related to the sequence port no for 



From now on for both DSI Ports A & C, the seq_port value has been
set to 0. seq_port value is parsed from Sequence block#53 of VBT.
So, for packets that needs to be read/write for DSI single link on
Port A and Port C will now be based on the DVO port from VBT block 2,
instead of seq_port.

Signed-off-by: default avatarGaurav K Singh <gaurav.k.singh@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 5f77eeb0

drivers/gpu/drm/i915/intel_dsi_panel_vbt.c

+9 −1
Original line number Diff line number Diff line
@@ -110,6 +110,14 @@ static u8 *mipi_exec_send_packet(struct intel_dsi *intel_dsi, u8 *data) 
	vc = (byte >> MIPI_VIRTUAL_CHANNEL_SHIFT) & 0x3;

	seq_port = (byte >> MIPI_PORT_SHIFT) & 0x3;



	/* For DSI single link on Port A & C, the seq_port value which is

	 * parsed from Sequence Block#53 of VBT has been set to 0

	 * Now, read/write of packets for the DSI single link on Port A and

	 * Port C will based on the DVO port from VBT block 2.

	 */

	if (intel_dsi->ports == (1 << PORT_C))

		port = PORT_C;

	else

		port = intel_dsi_seq_port_to_port(seq_port);

	/* LP or HS mode */

	intel_dsi->hs = mode;