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Commit f8d863cb authored by H Hartley Sweeten's avatar H Hartley Sweeten Committed by Greg Kroah-Hartman
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staging: comedi: adl_pci9111: prefer using the BIT macro 



As suggested by checkpatch.pl, use the BIT macro to define the
register bits.

Signed-off-by: default avatarH Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: default avatarIan Abbott <abbotti@mev.co.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent c9f6bb96

drivers/staging/comedi/drivers/adl_pci9111.c

+14 −14
Original line number Diff line number Diff line
@@ -89,23 +89,23 @@ a multiple of chanlist_len*convert_arg. 
#define PCI9111_EDIO_REG		0x04

#define PCI9111_AI_CHANNEL_REG		0x06

#define PCI9111_AI_RANGE_STAT_REG	0x08

#define PCI9111_AI_STAT_AD_BUSY		(1 << 7)

#define PCI9111_AI_STAT_FF_FF		(1 << 6)

#define PCI9111_AI_STAT_FF_HF		(1 << 5)

#define PCI9111_AI_STAT_FF_EF		(1 << 4)

#define PCI9111_AI_STAT_AD_BUSY		BIT(7)

#define PCI9111_AI_STAT_FF_FF		BIT(6)

#define PCI9111_AI_STAT_FF_HF		BIT(5)

#define PCI9111_AI_STAT_FF_EF		BIT(4)

#define PCI9111_AI_RANGE_MASK		(7 << 0)

#define PCI9111_AI_TRIG_CTRL_REG	0x0a

#define PCI9111_AI_TRIG_CTRL_TRGEVENT	(1 << 5)

#define PCI9111_AI_TRIG_CTRL_POTRG	(1 << 4)

#define PCI9111_AI_TRIG_CTRL_PTRG	(1 << 3)

#define PCI9111_AI_TRIG_CTRL_ETIS	(1 << 2)

#define PCI9111_AI_TRIG_CTRL_TPST	(1 << 1)

#define PCI9111_AI_TRIG_CTRL_ASCAN	(1 << 0)

#define PCI9111_AI_TRIG_CTRL_TRGEVENT	BIT(5)

#define PCI9111_AI_TRIG_CTRL_POTRG	BIT(4)

#define PCI9111_AI_TRIG_CTRL_PTRG	BIT(3)

#define PCI9111_AI_TRIG_CTRL_ETIS	BIT(2)

#define PCI9111_AI_TRIG_CTRL_TPST	BIT(1)

#define PCI9111_AI_TRIG_CTRL_ASCAN	BIT(0)

#define PCI9111_INT_CTRL_REG		0x0c

#define PCI9111_INT_CTRL_ISC2		(1 << 3)

#define PCI9111_INT_CTRL_FFEN		(1 << 2)

#define PCI9111_INT_CTRL_ISC1		(1 << 1)

#define PCI9111_INT_CTRL_ISC0		(1 << 0)

#define PCI9111_INT_CTRL_ISC2		BIT(3)

#define PCI9111_INT_CTRL_FFEN		BIT(2)

#define PCI9111_INT_CTRL_ISC1		BIT(1)

#define PCI9111_INT_CTRL_ISC0		BIT(0)

#define PCI9111_SOFT_TRIG_REG		0x0e

#define PCI9111_8254_BASE_REG		0x40

#define PCI9111_INT_CLR_REG		0x48