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Commit f8610d49 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "msm: kgsl: Add support for efuse based LM ISENSE slope calculation"

parents fffe9ab6 2a3a44a5

drivers/gpu/msm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -2,11 +2,11 @@ 
config QCOM_KGSL

	tristate "Qualcomm Technologies, Inc. 3D Graphics driver"

	depends on ARCH_QCOM

	depends on QCOM_QFPROM

	select GENERIC_ALLOCATOR

	select FW_LOADER

	select PM_DEVFREQ

	select QCOM_SCM

	select NVMEM

	select DEVFREQ_GOV_SIMPLE_ONDEMAND

	select DEVFREQ_GOV_PERFORMANCE

	select DEVFREQ_GOV_QCOM_ADRENO_TZ

drivers/gpu/msm/adreno.c

+18 −1
Original line number Diff line number Diff line
@@ -1337,6 +1337,23 @@ static int adreno_read_speed_bin(struct platform_device *pdev, 
	return 0;

}



static int adreno_probe_efuse(struct platform_device *pdev,

					struct adreno_device *adreno_dev)

{

	int ret;



	ret = adreno_read_speed_bin(pdev, adreno_dev);

	if (ret)

		return ret;



	ret = nvmem_cell_read_u32(&pdev->dev, "isense_slope",

					&adreno_dev->lm_slope);

	if (ret && ret != -ENOENT)

		return ret;



	return 0;

}



static int adreno_probe(struct platform_device *pdev)

{

	const struct of_device_id *of_id;
@@ -1364,7 +1381,7 @@ static int adreno_probe(struct platform_device *pdev) 


	adreno_update_soc_hw_revision_quirks(adreno_dev, pdev);



	status = adreno_read_speed_bin(pdev, adreno_dev);

	status = adreno_probe_efuse(pdev, adreno_dev);

	if (status)

		return status;

drivers/gpu/msm/adreno.h

+2 −0
Original line number Diff line number Diff line
@@ -443,6 +443,7 @@ enum gpu_coresight_sources { 
 * @lm_limit: limiting value for LM

 * @lm_threshold_count: register value for counter for lm threshold breakin

 * @lm_threshold_cross: number of current peaks exceeding threshold

 * @lm_slope: Slope value in the fused register for LM

 * @ifpc_count: Number of times the GPU went into IFPC

 * @speed_bin: Indicate which power level set to use

 * @highest_bank_bit: Value of the highest bank bit
@@ -518,6 +519,7 @@ struct adreno_device { 
	uint32_t lm_limit;

	uint32_t lm_threshold_count;

	uint32_t lm_threshold_cross;

	u32 lm_slope;

	uint32_t ifpc_count;



	unsigned int speed_bin;

drivers/gpu/msm/kgsl_hfi.c

+26 −6
Original line number Diff line number Diff line
@@ -644,6 +644,29 @@ static int hfi_verify_fw_version(struct kgsl_device *device, 
	return 0;

}



static int hfi_send_lm_feature_ctrl(struct gmu_device *gmu,

		struct adreno_device *adreno_dev)

{

	struct hfi_set_value_cmd req = {

		.type = HFI_VALUE_LM_CS0,

		.subtype = 0,

		.data = adreno_dev->lm_slope,

	};

	struct kgsl_device *device = &adreno_dev->dev;

	int ret;



	if (!test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag))

		return 0;



	ret = hfi_send_feature_ctrl(gmu, HFI_FEATURE_LM, 1,

			device->pwrctrl.throttle_mask);



	if (!ret)

		ret = hfi_send_req(gmu, H2F_MSG_SET_VALUE, &req);



	return ret;

}



static int hfi_send_acd_feature_ctrl(struct gmu_device *gmu,

		struct adreno_device *adreno_dev)

{
@@ -723,12 +746,9 @@ int hfi_start(struct kgsl_device *device, 
		if (result)

			return result;



		if (test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) {

			result = hfi_send_feature_ctrl(gmu, HFI_FEATURE_LM, 1,

					device->pwrctrl.throttle_mask);

		result = hfi_send_lm_feature_ctrl(gmu, adreno_dev);

		if (result)

			return result;

		}



		result = hfi_send_core_fw_start(gmu);

		if (result)

drivers/gpu/msm/kgsl_hfi.h

+1 −0
Original line number Diff line number Diff line
@@ -96,6 +96,7 @@ struct hfi_queue_table; 
#define HFI_VALUE_LOG_EVENT_ON		112

#define HFI_VALUE_LOG_EVENT_OFF		113

#define HFI_VALUE_DCVS_OBJ		114

#define HFI_VALUE_LM_CS0		115



#define HFI_VALUE_GLOBAL_TOKEN		0xFFFFFFFF