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Commit f84d595a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arc-4.15-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc 

Pull ARC fixes from Vineet Gupta:

 - platform updates for setting up clock correctly

 - fixes to accomodate newer gcc (__builtin_trap, removed inline asm
   modifier)

 - other fixes

* tag 'arc-4.15-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc:
  ARC: handle gcc generated __builtin_trap for older compiler
  ARC: handle gcc generated __builtin_trap()
  ARC: uaccess: dont use "l" gcc inline asm constraint modifier
  ARC: [plat-axs103] refactor the quad core DT quirk code
  ARC: [plat-axs103]: Set initial core pll output frequency
  ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
  ARC: [plat-hsdk]: Set initial core pll output frequency
  ARC: [plat-hsdk] Switch DisplayLink driver from fbdev to DRM
  arc: do not use __print_symbol()
  ARC: Fix detection of dual-issue enabled
parents 89876f27 af1be2e2

arch/arc/boot/dts/axc003.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -35,6 +35,14 @@ 
			reg = <0x80 0x10>, <0x100 0x10>;

			#clock-cells = <0>;

			clocks = <&input_clk>;



			/*

			 * Set initial core pll output frequency to 90MHz.

			 * It will be applied at the core pll driver probing

			 * on early boot.

			 */

			assigned-clocks = <&core_clk>;

			assigned-clock-rates = <90000000>;

		};



		core_intc: archs-intc@cpu {

arch/arc/boot/dts/axc003_idu.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -35,6 +35,14 @@ 
			reg = <0x80 0x10>, <0x100 0x10>;

			#clock-cells = <0>;

			clocks = <&input_clk>;



			/*

			 * Set initial core pll output frequency to 100MHz.

			 * It will be applied at the core pll driver probing

			 * on early boot.

			 */

			assigned-clocks = <&core_clk>;

			assigned-clock-rates = <100000000>;

		};



		core_intc: archs-intc@cpu {

arch/arc/boot/dts/hsdk.dts

+8 −0
Original line number Diff line number Diff line
@@ -114,6 +114,14 @@ 
			reg = <0x00 0x10>, <0x14B8 0x4>;

			#clock-cells = <0>;

			clocks = <&input_clk>;



			/*

			 * Set initial core pll output frequency to 1GHz.

			 * It will be applied at the core pll driver probing

			 * on early boot.

			 */

			assigned-clocks = <&core_clk>;

			assigned-clock-rates = <1000000000>;

		};



		serial: serial@5000 {

arch/arc/configs/hsdk_defconfig

+3 −2
Original line number Diff line number Diff line
@@ -49,10 +49,11 @@ CONFIG_SERIAL_8250_DW=y 
CONFIG_SERIAL_OF_PLATFORM=y

# CONFIG_HW_RANDOM is not set

# CONFIG_HWMON is not set

CONFIG_DRM=y

# CONFIG_DRM_FBDEV_EMULATION is not set

CONFIG_DRM_UDL=y

CONFIG_FB=y

CONFIG_FB_UDL=y

CONFIG_FRAMEBUFFER_CONSOLE=y

CONFIG_USB=y

CONFIG_USB_EHCI_HCD=y

CONFIG_USB_EHCI_HCD_PLATFORM=y

CONFIG_USB_OHCI_HCD=y

arch/arc/include/asm/uaccess.h

+3 −2
Original line number Diff line number Diff line
@@ -668,6 +668,7 @@ __arc_strncpy_from_user(char *dst, const char __user *src, long count) 
		return 0;



	__asm__ __volatile__(

	"	mov	lp_count, %5		\n"

	"	lp	3f			\n"

	"1:	ldb.ab  %3, [%2, 1]		\n"

	"	breq.d	%3, 0, 3f               \n"
@@ -684,8 +685,8 @@ __arc_strncpy_from_user(char *dst, const char __user *src, long count) 
	"	.word   1b, 4b			\n"

	"	.previous			\n"

	: "+r"(res), "+r"(dst), "+r"(src), "=r"(val)

	: "g"(-EFAULT), "l"(count)

	: "memory");

	: "g"(-EFAULT), "r"(count)

	: "lp_count", "lp_start", "lp_end", "memory");



	return res;

}