ARM: dts: msm: Use L3 Cache Miss event for DDR latency devices.

Use L3 Cache miss event to caluculate the IPM ratio for the
DDR latency devices temporarily till the LLCC Cache miss events
are working on kona.

Change-Id: I642bd2b5b4526dcb9d1f31b019d25cf5654e3d9f
Signed-off-by: Rama Aparna Mallavarapu <aparnam@codeaurora.org>