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Commit f7f36c1f authored by Eric Bernstein's avatar Eric Bernstein Committed by Alex Deucher
Browse files

drm/amd/display: OPP DPG test pattern 



Create opp_set_test_pattern function with similar interface
and implementation as timing generator test pattern.

Signed-off-by: default avatarEric Bernstein <eric.bernstein@amd.com>
Reviewed-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b6295960

drivers/gpu/drm/amd/display/dc/inc/hw/hw_shared.h

+37 −0
Original line number Diff line number Diff line
@@ -178,4 +178,41 @@ struct dc_bias_and_scale { 
	uint16_t bias_blue;

};



enum test_pattern_dyn_range {

	TEST_PATTERN_DYN_RANGE_VESA = 0,

	TEST_PATTERN_DYN_RANGE_CEA

};



enum test_pattern_mode {

	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,

	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,

	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,

	TEST_PATTERN_MODE_VERTICALBARS,

	TEST_PATTERN_MODE_HORIZONTALBARS,

	TEST_PATTERN_MODE_SINGLERAMP_RGB,

	TEST_PATTERN_MODE_DUALRAMP_RGB

};



enum test_pattern_color_format {

	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,

	TEST_PATTERN_COLOR_FORMAT_BPC_8,

	TEST_PATTERN_COLOR_FORMAT_BPC_10,

	TEST_PATTERN_COLOR_FORMAT_BPC_12

};



enum controller_dp_test_pattern {

	CONTROLLER_DP_TEST_PATTERN_D102 = 0,

	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,

	CONTROLLER_DP_TEST_PATTERN_PRBS7,

	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,

	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,

	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,

	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,

	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,

	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,

	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,

	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA

};



#endif /* __DAL_HW_SHARED_H__ */

drivers/gpu/drm/amd/display/dc/inc/hw/opp.h

+4 −1
Original line number Diff line number Diff line
@@ -284,7 +284,10 @@ struct opp_funcs { 


	void (*opp_set_test_pattern)(

			struct output_pixel_processor *opp,

			bool enable);

			enum controller_dp_test_pattern test_pattern,

			enum dc_color_depth color_depth,

			int width,

			int height);



	void (*opp_dpg_blank_enable)(

			struct output_pixel_processor *opp,

drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h

+2 −37
Original line number Diff line number Diff line
@@ -26,6 +26,8 @@ 
#ifndef __DAL_TIMING_GENERATOR_TYPES_H__

#define __DAL_TIMING_GENERATOR_TYPES_H__



#include "hw_shared.h"



struct dc_bios;



/* Contains CRTC vertical/horizontal pixel counters */
@@ -50,43 +52,6 @@ struct drr_params { 
#define LEFT_EYE_3D_PRIMARY_SURFACE 1

#define RIGHT_EYE_3D_PRIMARY_SURFACE 0



enum test_pattern_dyn_range {

	TEST_PATTERN_DYN_RANGE_VESA = 0,

	TEST_PATTERN_DYN_RANGE_CEA

};



enum test_pattern_mode {

	TEST_PATTERN_MODE_COLORSQUARES_RGB = 0,

	TEST_PATTERN_MODE_COLORSQUARES_YCBCR601,

	TEST_PATTERN_MODE_COLORSQUARES_YCBCR709,

	TEST_PATTERN_MODE_VERTICALBARS,

	TEST_PATTERN_MODE_HORIZONTALBARS,

	TEST_PATTERN_MODE_SINGLERAMP_RGB,

	TEST_PATTERN_MODE_DUALRAMP_RGB

};



enum test_pattern_color_format {

	TEST_PATTERN_COLOR_FORMAT_BPC_6 = 0,

	TEST_PATTERN_COLOR_FORMAT_BPC_8,

	TEST_PATTERN_COLOR_FORMAT_BPC_10,

	TEST_PATTERN_COLOR_FORMAT_BPC_12

};



enum controller_dp_test_pattern {

	CONTROLLER_DP_TEST_PATTERN_D102 = 0,

	CONTROLLER_DP_TEST_PATTERN_SYMBOLERROR,

	CONTROLLER_DP_TEST_PATTERN_PRBS7,

	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES,

	CONTROLLER_DP_TEST_PATTERN_VERTICALBARS,

	CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS,

	CONTROLLER_DP_TEST_PATTERN_COLORRAMP,

	CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

	CONTROLLER_DP_TEST_PATTERN_RESERVED_8,

	CONTROLLER_DP_TEST_PATTERN_RESERVED_9,

	CONTROLLER_DP_TEST_PATTERN_RESERVED_A,

	CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA

};



enum crtc_state {

	CRTC_STATE_VBLANK = 0,

	CRTC_STATE_VACTIVE