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Commit f71ddc58 authored by Alexandru M Stan's avatar Alexandru M Stan Committed by Ulf Hansson
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ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices 



The drive/sample clocks can be phase shifted.  The drive clock
could be used in a future patch to adjust hold times.  The sample
clock is used for tuning.

Signed-off-by: default avatarAlexandru M Stan <amstan@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent cbb79e43

arch/arm/boot/dts/rk3288.dtsi

+12 −8
Original line number Diff line number Diff line
@@ -222,8 +222,9 @@ 
	sdmmc: dwmmc@ff0c0000 {

		compatible = "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 150000000>;

		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;

		clock-names = "biu", "ciu";

		clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,

			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		fifo-depth = <0x100>;

		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;

		reg = <0xff0c0000 0x4000>;
@@ -233,8 +234,9 @@ 
	sdio0: dwmmc@ff0d0000 {

		compatible = "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 150000000>;

		clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>;

		clock-names = "biu", "ciu";

		clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,

			 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		fifo-depth = <0x100>;

		interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;

		reg = <0xff0d0000 0x4000>;
@@ -244,8 +246,9 @@ 
	sdio1: dwmmc@ff0e0000 {

		compatible = "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 150000000>;

		clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>;

		clock-names = "biu", "ciu";

		clocks = <&cru HCLK_SDIO1>, <&cru SCLK_SDIO1>,

			 <&cru SCLK_SDIO1_DRV>, <&cru SCLK_SDIO1_SAMPLE>;

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		fifo-depth = <0x100>;

		interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;

		reg = <0xff0e0000 0x4000>;
@@ -255,8 +258,9 @@ 
	emmc: dwmmc@ff0f0000 {

		compatible = "rockchip,rk3288-dw-mshc";

		clock-freq-min-max = <400000 150000000>;

		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;

		clock-names = "biu", "ciu";

		clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,

			 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;

		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";

		fifo-depth = <0x100>;

		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;

		reg = <0xff0f0000 0x4000>;