Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f6e51c35 authored by Dave Jiang's avatar Dave Jiang Committed by Jon Mason
Browse files

ntb: intel: split out the gen3 code 



Move the Intel hw gen3 code to its own source file. The ntb_hw_intel.c was
getting too large and makes it hard to maintain with future hardware
changes.

Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Signed-off-by: default avatarJon Mason <jdmason@kudzu.us>
parent a9065055

drivers/ntb/hw/intel/Makefile

+1 −0
Original line number Diff line number Diff line 
obj-$(CONFIG_NTB_INTEL) += ntb_hw_intel.o

ntb_hw_intel-y := ntb_hw_gen1.o ntb_hw_gen3.o

drivers/ntb/hw/intel/ntb_hw_intel.c→drivers/ntb/hw/intel/ntb_hw_gen1.c

+37 −657
Original line number Diff line number Diff line
@@ -60,9 +60,9 @@ 
#include <linux/slab.h>

#include <linux/ntb.h>



#include "ntb_hw_intel.h"

#include "ntb_hw_gen1.h"

#include "ntb_hw_gen3.h"

#include "ntb_hw_intel.h"



#define NTB_NAME	"ntb_hw_intel"

#define NTB_DESC	"Intel(R) PCI-E Non-Transparent Bridge Driver"
@@ -82,14 +82,7 @@ static const struct intel_ntb_alt_reg xeon_sec_reg; 
static const struct intel_ntb_alt_reg xeon_b2b_reg;

static const struct intel_ntb_xlat_reg xeon_pri_xlat;

static const struct intel_ntb_xlat_reg xeon_sec_xlat;

static struct intel_b2b_addr xeon_b2b_usd_addr;

static struct intel_b2b_addr xeon_b2b_dsd_addr;

static const struct intel_ntb_reg skx_reg;

static const struct intel_ntb_alt_reg skx_pri_reg;

static const struct intel_ntb_alt_reg skx_b2b_reg;

static const struct intel_ntb_xlat_reg skx_sec_xlat;

static const struct ntb_dev_ops intel_ntb_ops;

static const struct ntb_dev_ops intel_ntb3_ops;



static const struct file_operations intel_ntb_debugfs_info;

static struct dentry *debugfs_dir;
@@ -148,68 +141,8 @@ module_param_named(xeon_b2b_dsd_bar5_addr32, 
MODULE_PARM_DESC(xeon_b2b_dsd_bar5_addr32,

		 "XEON B2B DSD split-BAR 5 32-bit address");



static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd);

static int xeon_init_isr(struct intel_ntb_dev *ndev);



#ifndef ioread64

#ifdef readq

#define ioread64 readq

#else

#define ioread64 _ioread64

static inline u64 _ioread64(void __iomem *mmio)

{

	u64 low, high;



	low = ioread32(mmio);

	high = ioread32(mmio + sizeof(u32));

	return low | (high << 32);

}

#endif

#endif



#ifndef iowrite64

#ifdef writeq

#define iowrite64 writeq

#else

#define iowrite64 _iowrite64

static inline void _iowrite64(u64 val, void __iomem *mmio)

{

	iowrite32(val, mmio);

	iowrite32(val >> 32, mmio + sizeof(u32));

}

#endif

#endif



static inline int pdev_is_xeon(struct pci_dev *pdev)

{

	switch (pdev->device) {

	case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:

	case PCI_DEVICE_ID_INTEL_NTB_SS_SNB:

	case PCI_DEVICE_ID_INTEL_NTB_SS_IVT:

	case PCI_DEVICE_ID_INTEL_NTB_SS_HSX:

	case PCI_DEVICE_ID_INTEL_NTB_SS_BDX:

	case PCI_DEVICE_ID_INTEL_NTB_PS_JSF:

	case PCI_DEVICE_ID_INTEL_NTB_PS_SNB:

	case PCI_DEVICE_ID_INTEL_NTB_PS_IVT:

	case PCI_DEVICE_ID_INTEL_NTB_PS_HSX:

	case PCI_DEVICE_ID_INTEL_NTB_PS_BDX:

	case PCI_DEVICE_ID_INTEL_NTB_B2B_JSF:

	case PCI_DEVICE_ID_INTEL_NTB_B2B_SNB:

	case PCI_DEVICE_ID_INTEL_NTB_B2B_IVT:

	case PCI_DEVICE_ID_INTEL_NTB_B2B_HSX:

	case PCI_DEVICE_ID_INTEL_NTB_B2B_BDX:

		return 1;

	}

	return 0;

}



static inline int pdev_is_skx_xeon(struct pci_dev *pdev)

{

	if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)

		return 1;



	return 0;

}

static int xeon_init_isr(struct intel_ntb_dev *ndev);



static inline void ndev_reset_unsafe_flags(struct intel_ntb_dev *ndev)

{
@@ -243,7 +176,7 @@ static inline int ndev_ignore_unsafe(struct intel_ntb_dev *ndev, 
	return !!flag;

}



static int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx)

int ndev_mw_to_bar(struct intel_ntb_dev *ndev, int idx)

{

	if (idx < 0 || idx >= ndev->mw_count)

		return -EINVAL;
@@ -270,7 +203,7 @@ static inline int ndev_db_addr(struct intel_ntb_dev *ndev, 
	return 0;

}



static inline u64 ndev_db_read(struct intel_ntb_dev *ndev,

u64 ndev_db_read(struct intel_ntb_dev *ndev,

			       void __iomem *mmio)

{

	if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB))
@@ -279,7 +212,7 @@ static inline u64 ndev_db_read(struct intel_ntb_dev *ndev, 
	return ndev->reg->db_ioread(mmio);

}



static inline int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,

int ndev_db_write(struct intel_ntb_dev *ndev, u64 db_bits,

				void __iomem *mmio)

{

	if (ndev_is_unsafe(ndev, NTB_UNSAFE_DB))
@@ -431,7 +364,7 @@ static irqreturn_t ndev_irq_isr(int irq, void *dev) 
	return ndev_interrupt(ndev, irq - ndev->ntb.pdev->irq);

}



static int ndev_init_isr(struct intel_ntb_dev *ndev,

int ndev_init_isr(struct intel_ntb_dev *ndev,

			 int msix_min, int msix_max,

			 int msix_shift, int total_shift)

{
@@ -559,169 +492,6 @@ static void ndev_deinit_isr(struct intel_ntb_dev *ndev) 
	}

}



static ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,

				      size_t count, loff_t *offp)

{

	struct intel_ntb_dev *ndev;

	void __iomem *mmio;

	char *buf;

	size_t buf_size;

	ssize_t ret, off;

	union { u64 v64; u32 v32; u16 v16; } u;



	ndev = filp->private_data;

	mmio = ndev->self_mmio;



	buf_size = min(count, 0x800ul);



	buf = kmalloc(buf_size, GFP_KERNEL);

	if (!buf)

		return -ENOMEM;



	off = 0;



	off += scnprintf(buf + off, buf_size - off,

			 "NTB Device Information:\n");



	off += scnprintf(buf + off, buf_size - off,

			 "Connection Topology -\t%s\n",

			 ntb_topo_string(ndev->ntb.topo));



	off += scnprintf(buf + off, buf_size - off,

			 "NTB CTL -\t\t%#06x\n", ndev->ntb_ctl);

	off += scnprintf(buf + off, buf_size - off,

			 "LNK STA -\t\t%#06x\n", ndev->lnk_sta);



	if (!ndev->reg->link_is_up(ndev))

		off += scnprintf(buf + off, buf_size - off,

				 "Link Status -\t\tDown\n");

	else {

		off += scnprintf(buf + off, buf_size - off,

				 "Link Status -\t\tUp\n");

		off += scnprintf(buf + off, buf_size - off,

				 "Link Speed -\t\tPCI-E Gen %u\n",

				 NTB_LNK_STA_SPEED(ndev->lnk_sta));

		off += scnprintf(buf + off, buf_size - off,

				 "Link Width -\t\tx%u\n",

				 NTB_LNK_STA_WIDTH(ndev->lnk_sta));

	}



	off += scnprintf(buf + off, buf_size - off,

			 "Memory Window Count -\t%u\n", ndev->mw_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Scratchpad Count -\t%u\n", ndev->spad_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Count -\t%u\n", ndev->db_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Vector Count -\t%u\n", ndev->db_vec_count);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Vector Shift -\t%u\n", ndev->db_vec_shift);



	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Valid Mask -\t%#llx\n", ndev->db_valid_mask);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Link Mask -\t%#llx\n", ndev->db_link_mask);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Mask Cached -\t%#llx\n", ndev->db_mask);



	u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_mask);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Mask -\t\t%#llx\n", u.v64);



	u.v64 = ndev_db_read(ndev, mmio + ndev->self_reg->db_bell);

	off += scnprintf(buf + off, buf_size - off,

			 "Doorbell Bell -\t\t%#llx\n", u.v64);



	off += scnprintf(buf + off, buf_size - off,

			 "\nNTB Incoming XLAT:\n");



	u.v64 = ioread64(mmio + SKX_IMBAR1XBASE_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR1XBASE -\t\t%#018llx\n", u.v64);



	u.v64 = ioread64(mmio + SKX_IMBAR2XBASE_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR2XBASE -\t\t%#018llx\n", u.v64);



	u.v64 = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR1XLMT -\t\t\t%#018llx\n", u.v64);



	u.v64 = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "IMBAR2XLMT -\t\t\t%#018llx\n", u.v64);



	if (ntb_topo_is_b2b(ndev->ntb.topo)) {

		off += scnprintf(buf + off, buf_size - off,

				 "\nNTB Outgoing B2B XLAT:\n");



		u.v64 = ioread64(mmio + SKX_EMBAR1XBASE_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR1XBASE -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + SKX_EMBAR2XBASE_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR2XBASE -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + SKX_EMBAR1XLMT_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR1XLMT -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + SKX_EMBAR2XLMT_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR2XLMT -\t\t%#018llx\n", u.v64);



		off += scnprintf(buf + off, buf_size - off,

				 "\nNTB Secondary BAR:\n");



		u.v64 = ioread64(mmio + SKX_EMBAR0_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR0 -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + SKX_EMBAR1_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR1 -\t\t%#018llx\n", u.v64);



		u.v64 = ioread64(mmio + SKX_EMBAR2_OFFSET);

		off += scnprintf(buf + off, buf_size - off,

				 "EMBAR2 -\t\t%#018llx\n", u.v64);

	}



	off += scnprintf(buf + off, buf_size - off,

			 "\nNTB Statistics:\n");



	u.v16 = ioread16(mmio + SKX_USMEMMISS_OFFSET);

	off += scnprintf(buf + off, buf_size - off,

			 "Upstream Memory Miss -\t%u\n", u.v16);



	off += scnprintf(buf + off, buf_size - off,

			 "\nNTB Hardware Errors:\n");



	if (!pci_read_config_word(ndev->ntb.pdev,

				  SKX_DEVSTS_OFFSET, &u.v16))

		off += scnprintf(buf + off, buf_size - off,

				 "DEVSTS -\t\t%#06x\n", u.v16);



	if (!pci_read_config_word(ndev->ntb.pdev,

				  SKX_LINK_STATUS_OFFSET, &u.v16))

		off += scnprintf(buf + off, buf_size - off,

				 "LNKSTS -\t\t%#06x\n", u.v16);



	if (!pci_read_config_dword(ndev->ntb.pdev,

				   SKX_UNCERRSTS_OFFSET, &u.v32))

		off += scnprintf(buf + off, buf_size - off,

				 "UNCERRSTS -\t\t%#06x\n", u.v32);



	if (!pci_read_config_dword(ndev->ntb.pdev,

				   SKX_CORERRSTS_OFFSET, &u.v32))

		off += scnprintf(buf + off, buf_size - off,

				 "CORERRSTS -\t\t%#06x\n", u.v32);



	ret = simple_read_from_buffer(ubuf, count, offp, buf, off);

	kfree(buf);

	return ret;

}



static ssize_t ndev_ntb_debugfs_read(struct file *filp, char __user *ubuf,

				     size_t count, loff_t *offp)

{
@@ -1025,7 +795,7 @@ static void ndev_deinit_debugfs(struct intel_ntb_dev *ndev) 
	debugfs_remove_recursive(ndev->debugfs_dir);

}



static int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx)

int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx)

{

	if (pidx != NTB_DEF_PEER_IDX)

		return -EINVAL;
@@ -1033,7 +803,7 @@ static int intel_ntb_mw_count(struct ntb_dev *ntb, int pidx) 
	return ntb_ndev(ntb)->mw_count;

}



static int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,

int intel_ntb_mw_get_align(struct ntb_dev *ntb, int pidx, int idx,

			   resource_size_t *addr_align,

			   resource_size_t *size_align,

			   resource_size_t *size_max)
@@ -1172,8 +942,7 @@ static int intel_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx, 
	return 0;

}



static u64 intel_ntb_link_is_up(struct ntb_dev *ntb,

				enum ntb_speed *speed,

u64 intel_ntb_link_is_up(struct ntb_dev *ntb, enum ntb_speed *speed,

			 enum ntb_width *width)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1226,7 +995,7 @@ static int intel_ntb_link_enable(struct ntb_dev *ntb, 
	return 0;

}



static int intel_ntb_link_disable(struct ntb_dev *ntb)

int intel_ntb_link_disable(struct ntb_dev *ntb)

{

	struct intel_ntb_dev *ndev;

	u32 ntb_cntl;
@@ -1250,13 +1019,13 @@ static int intel_ntb_link_disable(struct ntb_dev *ntb) 
	return 0;

}



static int intel_ntb_peer_mw_count(struct ntb_dev *ntb)

int intel_ntb_peer_mw_count(struct ntb_dev *ntb)

{

	/* Numbers of inbound and outbound memory windows match */

	return ntb_ndev(ntb)->mw_count;

}



static int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx,

int intel_ntb_peer_mw_get_addr(struct ntb_dev *ntb, int idx,

			       phys_addr_t *base, resource_size_t *size)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1285,12 +1054,12 @@ static int intel_ntb_db_is_unsafe(struct ntb_dev *ntb) 
	return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_DB);

}



static u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb)

u64 intel_ntb_db_valid_mask(struct ntb_dev *ntb)

{

	return ntb_ndev(ntb)->db_valid_mask;

}



static int intel_ntb_db_vector_count(struct ntb_dev *ntb)

int intel_ntb_db_vector_count(struct ntb_dev *ntb)

{

	struct intel_ntb_dev *ndev;
@@ -1299,7 +1068,7 @@ static int intel_ntb_db_vector_count(struct ntb_dev *ntb) 
	return ndev->db_vec_count;

}



static u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector)

u64 intel_ntb_db_vector_mask(struct ntb_dev *ntb, int db_vector)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1327,7 +1096,7 @@ static int intel_ntb_db_clear(struct ntb_dev *ntb, u64 db_bits) 
			     ndev->self_reg->db_bell);

}



static int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits)

int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1336,7 +1105,7 @@ static int intel_ntb_db_set_mask(struct ntb_dev *ntb, u64 db_bits) 
				ndev->self_reg->db_mask);

}



static int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits)

int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1345,8 +1114,7 @@ static int intel_ntb_db_clear_mask(struct ntb_dev *ntb, u64 db_bits) 
				  ndev->self_reg->db_mask);

}



static int intel_ntb_peer_db_addr(struct ntb_dev *ntb,

				  phys_addr_t *db_addr,

int intel_ntb_peer_db_addr(struct ntb_dev *ntb, phys_addr_t *db_addr,

			   resource_size_t *db_size)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1364,12 +1132,12 @@ static int intel_ntb_peer_db_set(struct ntb_dev *ntb, u64 db_bits) 
			     ndev->peer_reg->db_bell);

}



static int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb)

int intel_ntb_spad_is_unsafe(struct ntb_dev *ntb)

{

	return ndev_ignore_unsafe(ntb_ndev(ntb), NTB_UNSAFE_SPAD);

}



static int intel_ntb_spad_count(struct ntb_dev *ntb)

int intel_ntb_spad_count(struct ntb_dev *ntb)

{

	struct intel_ntb_dev *ndev;
@@ -1378,7 +1146,7 @@ static int intel_ntb_spad_count(struct ntb_dev *ntb) 
	return ndev->spad_count;

}



static u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx)

u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1387,8 +1155,7 @@ static u32 intel_ntb_spad_read(struct ntb_dev *ntb, int idx) 
			      ndev->self_reg->spad);

}



static int intel_ntb_spad_write(struct ntb_dev *ntb,

				int idx, u32 val)

int intel_ntb_spad_write(struct ntb_dev *ntb, int idx, u32 val)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1397,7 +1164,7 @@ static int intel_ntb_spad_write(struct ntb_dev *ntb, 
			       ndev->self_reg->spad);

}



static int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx,

int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx,

			     phys_addr_t *spad_addr)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1406,7 +1173,7 @@ static int intel_ntb_peer_spad_addr(struct ntb_dev *ntb, int pidx, int sidx, 
			      ndev->peer_reg->spad);

}



static u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx)

u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1415,8 +1182,8 @@ static u32 intel_ntb_peer_spad_read(struct ntb_dev *ntb, int pidx, int sidx) 
			      ndev->peer_reg->spad);

}



static int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx,

				     int sidx, u32 val)

int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, int sidx,

			      u32 val)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);
@@ -1425,336 +1192,6 @@ static int intel_ntb_peer_spad_write(struct ntb_dev *ntb, int pidx, 
			       ndev->peer_reg->spad);

}



/* Skylake Xeon NTB */



static int skx_poll_link(struct intel_ntb_dev *ndev)

{

	u16 reg_val;

	int rc;



	ndev->reg->db_iowrite(ndev->db_link_mask,

			      ndev->self_mmio +

			      ndev->self_reg->db_clear);



	rc = pci_read_config_word(ndev->ntb.pdev,

				  SKX_LINK_STATUS_OFFSET, &reg_val);

	if (rc)

		return 0;



	if (reg_val == ndev->lnk_sta)

		return 0;



	ndev->lnk_sta = reg_val;



	return 1;

}



static u64 skx_db_ioread(void __iomem *mmio)

{

	return ioread64(mmio);

}



static void skx_db_iowrite(u64 bits, void __iomem *mmio)

{

	iowrite64(bits, mmio);

}



static int skx_init_isr(struct intel_ntb_dev *ndev)

{

	int i;



	/*

	 * The MSIX vectors and the interrupt status bits are not lined up

	 * on Skylake. By default the link status bit is bit 32, however it

	 * is by default MSIX vector0. We need to fixup to line them up.

	 * The vectors at reset is 1-32,0. We need to reprogram to 0-32.

	 */



	for (i = 0; i < SKX_DB_MSIX_VECTOR_COUNT; i++)

		iowrite8(i, ndev->self_mmio + SKX_INTVEC_OFFSET + i);



	/* move link status down one as workaround */

	if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) {

		iowrite8(SKX_DB_MSIX_VECTOR_COUNT - 2,

			 ndev->self_mmio + SKX_INTVEC_OFFSET +

			 (SKX_DB_MSIX_VECTOR_COUNT - 1));

	}



	return ndev_init_isr(ndev, SKX_DB_MSIX_VECTOR_COUNT,

			     SKX_DB_MSIX_VECTOR_COUNT,

			     SKX_DB_MSIX_VECTOR_SHIFT,

			     SKX_DB_TOTAL_SHIFT);

}



static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,

			    const struct intel_b2b_addr *addr,

			    const struct intel_b2b_addr *peer_addr)

{

	struct pci_dev *pdev;

	void __iomem *mmio;

	phys_addr_t bar_addr;



	pdev = ndev->ntb.pdev;

	mmio = ndev->self_mmio;



	/* setup incoming bar limits == base addrs (zero length windows) */

	bar_addr = addr->bar2_addr64;

	iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET);

	bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET);

	dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);



	bar_addr = addr->bar4_addr64;

	iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET);

	bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET);

	dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);



	/* zero incoming translation addrs */

	iowrite64(0, mmio + SKX_IMBAR1XBASE_OFFSET);

	iowrite64(0, mmio + SKX_IMBAR2XBASE_OFFSET);



	ndev->peer_mmio = ndev->self_mmio;



	return 0;

}



static int skx_init_ntb(struct intel_ntb_dev *ndev)

{

	int rc;





	ndev->mw_count = XEON_MW_COUNT;

	ndev->spad_count = SKX_SPAD_COUNT;

	ndev->db_count = SKX_DB_COUNT;

	ndev->db_link_mask = SKX_DB_LINK_BIT;



	/* DB fixup for using 31 right now */

	if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)

		ndev->db_link_mask |= BIT_ULL(31);



	switch (ndev->ntb.topo) {

	case NTB_TOPO_B2B_USD:

	case NTB_TOPO_B2B_DSD:

		ndev->self_reg = &skx_pri_reg;

		ndev->peer_reg = &skx_b2b_reg;

		ndev->xlat_reg = &skx_sec_xlat;



		if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {

			rc = skx_setup_b2b_mw(ndev,

					      &xeon_b2b_dsd_addr,

					      &xeon_b2b_usd_addr);

		} else {

			rc = skx_setup_b2b_mw(ndev,

					      &xeon_b2b_usd_addr,

					      &xeon_b2b_dsd_addr);

		}



		if (rc)

			return rc;



		/* Enable Bus Master and Memory Space on the secondary side */

		iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,

			  ndev->self_mmio + SKX_SPCICMD_OFFSET);



		break;



	default:

		return -EINVAL;

	}



	ndev->db_valid_mask = BIT_ULL(ndev->db_count) - 1;



	ndev->reg->db_iowrite(ndev->db_valid_mask,

			      ndev->self_mmio +

			      ndev->self_reg->db_mask);



	return 0;

}



static int skx_init_dev(struct intel_ntb_dev *ndev)

{

	struct pci_dev *pdev;

	u8 ppd;

	int rc;



	pdev = ndev->ntb.pdev;



	ndev->reg = &skx_reg;



	rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);

	if (rc)

		return -EIO;



	ndev->ntb.topo = xeon_ppd_topo(ndev, ppd);

	dev_dbg(&pdev->dev, "ppd %#x topo %s\n", ppd,

		ntb_topo_string(ndev->ntb.topo));

	if (ndev->ntb.topo == NTB_TOPO_NONE)

		return -EINVAL;



	if (pdev_is_skx_xeon(pdev))

		ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD;



	rc = skx_init_ntb(ndev);

	if (rc)

		return rc;



	return skx_init_isr(ndev);

}



static int intel_ntb3_link_enable(struct ntb_dev *ntb,

				  enum ntb_speed max_speed,

				  enum ntb_width max_width)

{

	struct intel_ntb_dev *ndev;

	u32 ntb_ctl;



	ndev = container_of(ntb, struct intel_ntb_dev, ntb);



	dev_dbg(&ntb->pdev->dev,

		"Enabling link with max_speed %d max_width %d\n",

		max_speed, max_width);



	if (max_speed != NTB_SPEED_AUTO)

		dev_dbg(&ntb->pdev->dev, "ignoring max_speed %d\n", max_speed);

	if (max_width != NTB_WIDTH_AUTO)

		dev_dbg(&ntb->pdev->dev, "ignoring max_width %d\n", max_width);



	ntb_ctl = ioread32(ndev->self_mmio + ndev->reg->ntb_ctl);

	ntb_ctl &= ~(NTB_CTL_DISABLE | NTB_CTL_CFG_LOCK);

	ntb_ctl |= NTB_CTL_P2S_BAR2_SNOOP | NTB_CTL_S2P_BAR2_SNOOP;

	ntb_ctl |= NTB_CTL_P2S_BAR4_SNOOP | NTB_CTL_S2P_BAR4_SNOOP;

	iowrite32(ntb_ctl, ndev->self_mmio + ndev->reg->ntb_ctl);



	return 0;

}

static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,

				   dma_addr_t addr, resource_size_t size)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);

	unsigned long xlat_reg, limit_reg;

	resource_size_t bar_size, mw_size;

	void __iomem *mmio;

	u64 base, limit, reg_val;

	int bar;



	if (pidx != NTB_DEF_PEER_IDX)

		return -EINVAL;



	if (idx >= ndev->b2b_idx && !ndev->b2b_off)

		idx += 1;



	bar = ndev_mw_to_bar(ndev, idx);

	if (bar < 0)

		return bar;



	bar_size = pci_resource_len(ndev->ntb.pdev, bar);



	if (idx == ndev->b2b_idx)

		mw_size = bar_size - ndev->b2b_off;

	else

		mw_size = bar_size;



	/* hardware requires that addr is aligned to bar size */

	if (addr & (bar_size - 1))

		return -EINVAL;



	/* make sure the range fits in the usable mw size */

	if (size > mw_size)

		return -EINVAL;



	mmio = ndev->self_mmio;

	xlat_reg = ndev->xlat_reg->bar2_xlat + (idx * 0x10);

	limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10);

	base = pci_resource_start(ndev->ntb.pdev, bar);



	/* Set the limit if supported, if size is not mw_size */

	if (limit_reg && size != mw_size)

		limit = base + size;

	else

		limit = base + mw_size;



	/* set and verify setting the translation address */

	iowrite64(addr, mmio + xlat_reg);

	reg_val = ioread64(mmio + xlat_reg);

	if (reg_val != addr) {

		iowrite64(0, mmio + xlat_reg);

		return -EIO;

	}



	dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXBASE: %#Lx\n", bar, reg_val);



	/* set and verify setting the limit */

	iowrite64(limit, mmio + limit_reg);

	reg_val = ioread64(mmio + limit_reg);

	if (reg_val != limit) {

		iowrite64(base, mmio + limit_reg);

		iowrite64(0, mmio + xlat_reg);

		return -EIO;

	}



	dev_dbg(&ntb->pdev->dev, "BAR %d IMBARXLMT: %#Lx\n", bar, reg_val);



	/* setup the EP */

	limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;

	base = ioread64(mmio + SKX_EMBAR1_OFFSET + (8 * idx));

	base &= ~0xf;



	if (limit_reg && size != mw_size)

		limit = base + size;

	else

		limit = base + mw_size;



	/* set and verify setting the limit */

	iowrite64(limit, mmio + limit_reg);

	reg_val = ioread64(mmio + limit_reg);

	if (reg_val != limit) {

		iowrite64(base, mmio + limit_reg);

		iowrite64(0, mmio + xlat_reg);

		return -EIO;

	}



	dev_dbg(&ntb->pdev->dev, "BAR %d EMBARXLMT: %#Lx\n", bar, reg_val);



	return 0;

}



static int intel_ntb3_peer_db_set(struct ntb_dev *ntb, u64 db_bits)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);

	int bit;



	if (db_bits & ~ndev->db_valid_mask)

		return -EINVAL;



	while (db_bits) {

		bit = __ffs(db_bits);

		iowrite32(1, ndev->peer_mmio +

				ndev->peer_reg->db_bell + (bit * 4));

		db_bits &= db_bits - 1;

	}



	return 0;

}



static u64 intel_ntb3_db_read(struct ntb_dev *ntb)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);



	return ndev_db_read(ndev,

			    ndev->self_mmio +

			    ndev->self_reg->db_clear);

}



static int intel_ntb3_db_clear(struct ntb_dev *ntb, u64 db_bits)

{

	struct intel_ntb_dev *ndev = ntb_ndev(ntb);



	return ndev_db_write(ndev, db_bits,

			     ndev->self_mmio +

			     ndev->self_reg->db_clear);

}



/* XEON */



static u64 xeon_db_ioread(void __iomem *mmio)

{

	return (u64)ioread16(mmio);
@@ -1787,7 +1224,7 @@ static int xeon_poll_link(struct intel_ntb_dev *ndev) 
	return 1;

}



static int xeon_link_is_up(struct intel_ntb_dev *ndev)

int xeon_link_is_up(struct intel_ntb_dev *ndev)

{

	if (ndev->ntb.topo == NTB_TOPO_SEC)

		return 1;
@@ -1795,7 +1232,7 @@ static int xeon_link_is_up(struct intel_ntb_dev *ndev) 
	return NTB_LNK_STA_ACTIVE(ndev->lnk_sta);

}



static inline enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)

enum ntb_topo xeon_ppd_topo(struct intel_ntb_dev *ndev, u8 ppd)

{

	switch (ppd & XEON_PPD_TOPO_MASK) {

	case XEON_PPD_TOPO_B2B_USD:
@@ -2539,50 +1976,20 @@ static const struct intel_ntb_xlat_reg xeon_sec_xlat = { 
	.bar2_xlat		= XEON_SBAR23XLAT_OFFSET,

};



static struct intel_b2b_addr xeon_b2b_usd_addr = {

struct intel_b2b_addr xeon_b2b_usd_addr = {

	.bar2_addr64		= XEON_B2B_BAR2_ADDR64,

	.bar4_addr64		= XEON_B2B_BAR4_ADDR64,

	.bar4_addr32		= XEON_B2B_BAR4_ADDR32,

	.bar5_addr32		= XEON_B2B_BAR5_ADDR32,

};



static struct intel_b2b_addr xeon_b2b_dsd_addr = {

struct intel_b2b_addr xeon_b2b_dsd_addr = {

	.bar2_addr64		= XEON_B2B_BAR2_ADDR64,

	.bar4_addr64		= XEON_B2B_BAR4_ADDR64,

	.bar4_addr32		= XEON_B2B_BAR4_ADDR32,

	.bar5_addr32		= XEON_B2B_BAR5_ADDR32,

};



static const struct intel_ntb_reg skx_reg = {

	.poll_link		= skx_poll_link,

	.link_is_up		= xeon_link_is_up,

	.db_ioread		= skx_db_ioread,

	.db_iowrite		= skx_db_iowrite,

	.db_size		= sizeof(u32),

	.ntb_ctl		= SKX_NTBCNTL_OFFSET,

	.mw_bar			= {2, 4},

};



static const struct intel_ntb_alt_reg skx_pri_reg = {

	.db_bell		= SKX_EM_DOORBELL_OFFSET,

	.db_clear		= SKX_IM_INT_STATUS_OFFSET,

	.db_mask		= SKX_IM_INT_DISABLE_OFFSET,

	.spad			= SKX_IM_SPAD_OFFSET,

};



static const struct intel_ntb_alt_reg skx_b2b_reg = {

	.db_bell		= SKX_IM_DOORBELL_OFFSET,

	.db_clear		= SKX_EM_INT_STATUS_OFFSET,

	.db_mask		= SKX_EM_INT_DISABLE_OFFSET,

	.spad			= SKX_B2B_SPAD_OFFSET,

};



static const struct intel_ntb_xlat_reg skx_sec_xlat = {

/*	.bar0_base		= SKX_EMBAR0_OFFSET, */

	.bar2_limit		= SKX_IMBAR1XLMT_OFFSET,

	.bar2_xlat		= SKX_IMBAR1XBASE_OFFSET,

};



/* operations for primary side of local ntb */

static const struct ntb_dev_ops intel_ntb_ops = {

	.mw_count		= intel_ntb_mw_count,
@@ -2612,33 +2019,6 @@ static const struct ntb_dev_ops intel_ntb_ops = { 
	.peer_spad_write	= intel_ntb_peer_spad_write,

};



static const struct ntb_dev_ops intel_ntb3_ops = {

	.mw_count		= intel_ntb_mw_count,

	.mw_get_align		= intel_ntb_mw_get_align,

	.mw_set_trans		= intel_ntb3_mw_set_trans,

	.peer_mw_count		= intel_ntb_peer_mw_count,

	.peer_mw_get_addr	= intel_ntb_peer_mw_get_addr,

	.link_is_up		= intel_ntb_link_is_up,

	.link_enable		= intel_ntb3_link_enable,

	.link_disable		= intel_ntb_link_disable,

	.db_valid_mask		= intel_ntb_db_valid_mask,

	.db_vector_count	= intel_ntb_db_vector_count,

	.db_vector_mask		= intel_ntb_db_vector_mask,

	.db_read		= intel_ntb3_db_read,

	.db_clear		= intel_ntb3_db_clear,

	.db_set_mask		= intel_ntb_db_set_mask,

	.db_clear_mask		= intel_ntb_db_clear_mask,

	.peer_db_addr		= intel_ntb_peer_db_addr,

	.peer_db_set		= intel_ntb3_peer_db_set,

	.spad_is_unsafe		= intel_ntb_spad_is_unsafe,

	.spad_count		= intel_ntb_spad_count,

	.spad_read		= intel_ntb_spad_read,

	.spad_write		= intel_ntb_spad_write,

	.peer_spad_addr		= intel_ntb_peer_spad_addr,

	.peer_spad_read		= intel_ntb_peer_spad_read,

	.peer_spad_write	= intel_ntb_peer_spad_write,

};



static const struct file_operations intel_ntb_debugfs_info = {

	.owner = THIS_MODULE,

	.open = simple_open,