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Commit f689e3ac authored by Mikko Tiihonen's avatar Mikko Tiihonen Committed by Alex Deucher
Browse files

drm/radeon: protect against div by 0 in backend setup 

Make sure at least one RB is enabled in
r6xx_remap_render_backend() to avoid an division by
zero in some corner cases.

See:
https://bugzilla.redhat.com/show_bug.cgi?id=892233



Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent f7eb9730

drivers/gpu/drm/radeon/r600.c

+5 −2
Original line number Original line Diff line number Diff line
@@ -1462,12 +1462,15 @@ u32 r6xx_remap_render_backend(struct radeon_device *rdev, 
			      u32 disabled_rb_mask)

			      u32 disabled_rb_mask)

{

{

	u32 rendering_pipe_num, rb_num_width, req_rb_num;

	u32 rendering_pipe_num, rb_num_width, req_rb_num;

	u32 pipe_rb_ratio, pipe_rb_remain;

	u32 pipe_rb_ratio, pipe_rb_remain, tmp;

	u32 data = 0, mask = 1 << (max_rb_num - 1);

	u32 data = 0, mask = 1 << (max_rb_num - 1);

	unsigned i, j;

	unsigned i, j;





	/* mask out the RBs that don't exist on that asic */

	/* mask out the RBs that don't exist on that asic */

	disabled_rb_mask |= (0xff << max_rb_num) & 0xff;

	tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);

	/* make sure at least one RB is available */

	if ((tmp & 0xff) != 0xff)

		disabled_rb_mask = tmp;





	rendering_pipe_num = 1 << tiling_pipe_num;

	rendering_pipe_num = 1 << tiling_pipe_num;

	req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);

	req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);