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Commit f6721e5c authored by Manu Gautam's avatar Manu Gautam Committed by Kishon Vijay Abraham I
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phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845 



QMP V3 UNI PHY is a single lane USB3 PHY without support
for DisplayPort (DP).
Main difference from DP combo QMPv3 PHY is that UNI PHY
doesn't have dual RX/TX lanes and no separate DP_COM
block for configuration related to type-c or DP.
Also remove "qcom,qmp-v3-usb3-phy" compatible string which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.

Reviewed-by: default avatarEvan Green <evgreen@chromium.org>
Signed-off-by: default avatarManu Gautam <mgautam@codeaurora.org>
Signed-off-by: default avatarKishon Vijay Abraham I <kishon@ti.com>
parent 7f080207

drivers/phy/qualcomm/phy-qcom-qmp.c

+146 −1
Original line number Diff line number Diff line
@@ -490,6 +490,118 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 
	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),

	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),

	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),

	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),

};



static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {

	/* FLL settings */

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),



	/* Lock Det settings */

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),



	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),



	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),



	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),

	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),

};





/* struct qmp_phy_cfg - per-PHY initialization config */

struct qmp_phy_cfg {

	/* phy-type - PCIE/UFS/USB */
@@ -766,6 +878,7 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 
	.pwrdn_ctrl		= SW_PWRDN,

	.mask_pcs_ready		= PHYSTATUS,



	.has_pwrdn_delay	= true,

	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,

	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,
@@ -774,6 +887,35 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 
	.rx_b_lane_offset	= 0x400,

};



static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {

	.type			= PHY_TYPE_USB3,

	.nlanes			= 1,



	.serdes_tbl		= qmp_v3_usb3_uniphy_serdes_tbl,

	.serdes_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),

	.tx_tbl			= qmp_v3_usb3_uniphy_tx_tbl,

	.tx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),

	.rx_tbl			= qmp_v3_usb3_uniphy_rx_tbl,

	.rx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),

	.pcs_tbl		= qmp_v3_usb3_uniphy_pcs_tbl,

	.pcs_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),

	.clk_list		= qmp_v3_phy_clk_l,

	.num_clks		= ARRAY_SIZE(qmp_v3_phy_clk_l),

	.reset_list		= msm8996_usb3phy_reset_l,

	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),

	.vreg_list		= msm8996_phy_vreg_l,

	.num_vregs		= ARRAY_SIZE(msm8996_phy_vreg_l),

	.regs			= qmp_v3_usb3phy_regs_layout,



	.start_ctrl		= SERDES_START | PCS_START,

	.pwrdn_ctrl		= SW_PWRDN,

	.mask_pcs_ready		= PHYSTATUS,



	.has_pwrdn_delay	= true,

	.pwrdn_delay_min	= POWER_DOWN_DELAY_US_MIN,

	.pwrdn_delay_max	= POWER_DOWN_DELAY_US_MAX,

};



static void qcom_qmp_phy_configure(void __iomem *base,

				   const unsigned int *regs,

				   const struct qmp_phy_init_tbl tbl[],
@@ -1375,8 +1517,11 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { 
		.compatible = "qcom,ipq8074-qmp-pcie-phy",

		.data = &ipq8074_pciephy_cfg,

	}, {

		.compatible = "qcom,qmp-v3-usb3-phy",

		.compatible = "qcom,sdm845-qmp-usb3-phy",

		.data = &qmp_v3_usb3phy_cfg,

	}, {

		.compatible = "qcom,sdm845-qmp-usb3-uni-phy",

		.data = &qmp_v3_usb3_uniphy_cfg,

	},

	{ },

};

drivers/phy/qualcomm/phy-qcom-qmp.h

+5 −0
Original line number Diff line number Diff line
@@ -214,6 +214,8 @@ 
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN		0x030

#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE	0x034

#define QSERDES_V3_RX_RX_TERM_BW			0x07c

#define QSERDES_V3_RX_VGA_CAL_CNTRL1			0x0bc

#define QSERDES_V3_RX_VGA_CAL_CNTRL2			0x0c0

#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB			0x0c8

#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB			0x0cc

#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2		0x0d4
@@ -227,6 +229,7 @@ 
#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL		0x10c

#define QSERDES_V3_RX_RX_BAND				0x110

#define QSERDES_V3_RX_RX_INTERFACE_MODE			0x11c

#define QSERDES_V3_RX_RX_MODE_00			0x164



/* Only for QMP V3 PHY - PCS registers */

#define QPHY_V3_PCS_POWER_DOWN_CONTROL			0x004
@@ -273,6 +276,8 @@ 
#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL			0x0d0

#define QPHY_V3_PCS_FLL_MAN_CODE			0x0d4

#define QPHY_V3_PCS_RX_SIGDET_LVL			0x1d8

#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1			0x20c

#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2			0x210



/* Only for QMP V3 PHY - PCS_MISC registers */

#define QPHY_V3_PCS_MISC_CLAMP_ENABLE			0x0c