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Commit f5e706ad authored by Sam Ravnborg's avatar Sam Ravnborg Committed by David S. Miller
Browse files

sparc: join the remaining header files 



With this commit all sparc64 header files are moved to asm-sparc.
The remaining files (71 files) were too different to be trivially
merged so divide them up in a _32.h and a _64.h file which
are both included from the file with no bit size.

The following script were used:
cd include
FILES=`wc -l asm-sparc64/*h | grep -v '^     1' | cut -b 20-`

for FILE in ${FILES}; do
  echo $FILE:
  BASE=`echo $FILE | cut -d '.' -f 1`
  FN32=${BASE}_32.h
  FN64=${BASE}_64.h
  GUARD=___ASM_SPARC_`echo $BASE | tr '-' '_' | tr [:lower:] [:upper:]`_H
  git mv asm-sparc/$FILE asm-sparc/$FN32
  git mv asm-sparc64/$FILE asm-sparc/$FN64
  echo git mv done
  printf "#ifndef %s\n" $GUARD                             >   asm-sparc/$FILE
  printf "#define %s\n" $GUARD                             >>  asm-sparc/$FILE
  printf "#if defined(__sparc__) && defined(__arch64__)\n" >>  asm-sparc/$FILE
  printf "#include <asm-sparc/%s>\n" $FN64                 >>  asm-sparc/$FILE
  printf "#else\n"                                         >>  asm-sparc/$FILE
  printf "#include <asm-sparc/%s>\n" $FN32                 >>  asm-sparc/$FILE
  printf "#endif\n"                                        >>  asm-sparc/$FILE
  printf "#endif\n"                                        >>  asm-sparc/$FILE
  git add asm-sparc/$FILE
  echo new file done
  printf "#include <asm-sparc/%s>\n" $FILE                 >  asm-sparc64/$FILE
  git add asm-sparc64/$FILE
  echo sparc64 file done
done

The guard contains three '_' to avoid conflict with existing guards.
In additing the two Kbuild files are emptied to avoid breaking
headers_* targets.
We will reintroduce the exported header files when the necessary
kbuild changes are merged.

Signed-off-by: default avatarSam Ravnborg <sam@ravnborg.org>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 5e3609f6

include/asm-sparc/Kbuild

+1 −22
Original line number Diff line number Diff line 
include include/asm-generic/Kbuild.asm



header-y += apc.h

header-y += asi.h

header-y += bpp.h

header-y += display7seg.h

header-y += envctrl.h

header-y += jsflash.h

header-y += openprom.h

header-y += openpromio.h

header-y += psrcompat.h

header-y += pstate.h

header-y += reg.h

header-y += traps.h

header-y += uctx.h

header-y += utrap.h

header-y += vfc_ioctls.h

header-y += watchdog.h



unifdef-y += fbio.h

unifdef-y += perfctr.h

unifdef-y += psr.h
 
# dummy file to avoid breaking make headers_install

include/asm-sparc/atomic.h

+6 −163
Original line number Diff line number Diff line 
/* atomic.h: These still suck, but the I-cache hit rate is higher.

 *

 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)

 * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)

 * Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)

 *

 * Additions by Keith M Wesolowski (wesolows@foobazco.org) based

 * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.

 */



#ifndef __ARCH_SPARC_ATOMIC__

#define __ARCH_SPARC_ATOMIC__



#include <linux/types.h>



typedef struct { volatile int counter; } atomic_t;



#ifdef __KERNEL__



#define ATOMIC_INIT(i)  { (i) }



extern int __atomic_add_return(int, atomic_t *);

extern int atomic_cmpxchg(atomic_t *, int, int);

#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

extern int atomic_add_unless(atomic_t *, int, int);

extern void atomic_set(atomic_t *, int);



#define atomic_read(v)          ((v)->counter)



#define atomic_add(i, v)	((void)__atomic_add_return( (int)(i), (v)))

#define atomic_sub(i, v)	((void)__atomic_add_return(-(int)(i), (v)))

#define atomic_inc(v)		((void)__atomic_add_return(        1, (v)))

#define atomic_dec(v)		((void)__atomic_add_return(       -1, (v)))



#define atomic_add_return(i, v)	(__atomic_add_return( (int)(i), (v)))

#define atomic_sub_return(i, v)	(__atomic_add_return(-(int)(i), (v)))

#define atomic_inc_return(v)	(__atomic_add_return(        1, (v)))

#define atomic_dec_return(v)	(__atomic_add_return(       -1, (v)))



#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)



/*

 * atomic_inc_and_test - increment and test

 * @v: pointer of type atomic_t

 *

 * Atomically increments @v by 1

 * and returns true if the result is zero, or false for all

 * other cases.

 */

#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)



#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)

#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)



#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)



/* This is the old 24-bit implementation.  It's still used internally

 * by some sparc-specific code, notably the semaphore implementation.

 */

typedef struct { volatile int counter; } atomic24_t;



#ifndef CONFIG_SMP



#define ATOMIC24_INIT(i)  { (i) }

#define atomic24_read(v)          ((v)->counter)

#define atomic24_set(v, i)        (((v)->counter) = i)



#ifndef ___ASM_SPARC_ATOMIC_H

#define ___ASM_SPARC_ATOMIC_H

#if defined(__sparc__) && defined(__arch64__)

#include <asm-sparc/atomic_64.h>

#else

/* We do the bulk of the actual work out of line in two common

 * routines in assembler, see arch/sparc/lib/atomic.S for the

 * "fun" details.

 *

 * For SMP the trick is you embed the spin lock byte within

 * the word, use the low byte so signedness is easily retained

 * via a quick arithmetic shift.  It looks like this:

 *

 *	----------------------------------------

 *	| signed 24-bit counter value |  lock  |  atomic_t

 *	----------------------------------------

 *	 31                          8 7      0

 */



#define ATOMIC24_INIT(i)	{ ((i) << 8) }



static inline int atomic24_read(const atomic24_t *v)

{

	int ret = v->counter;



	while(ret & 0xff)

		ret = v->counter;



	return ret >> 8;

}



#define atomic24_set(v, i)	(((v)->counter) = ((i) << 8))

#include <asm-sparc/atomic_32.h>

#endif

#endif
 


static inline int __atomic24_add(int i, atomic24_t *v)

{

	register volatile int *ptr asm("g1");

	register int increment asm("g2");

	register int tmp1 asm("g3");

	register int tmp2 asm("g4");

	register int tmp3 asm("g7");



	ptr = &v->counter;

	increment = i;



	__asm__ __volatile__(

	"mov	%%o7, %%g4\n\t"

	"call	___atomic24_add\n\t"

	" add	%%o7, 8, %%o7\n"

	: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)

	: "0" (increment), "r" (ptr)

	: "memory", "cc");



	return increment;

}



static inline int __atomic24_sub(int i, atomic24_t *v)

{

	register volatile int *ptr asm("g1");

	register int increment asm("g2");

	register int tmp1 asm("g3");

	register int tmp2 asm("g4");

	register int tmp3 asm("g7");



	ptr = &v->counter;

	increment = i;



	__asm__ __volatile__(

	"mov	%%o7, %%g4\n\t"

	"call	___atomic24_sub\n\t"

	" add	%%o7, 8, %%o7\n"

	: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)

	: "0" (increment), "r" (ptr)

	: "memory", "cc");



	return increment;

}



#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))

#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))



#define atomic24_dec_return(v) __atomic24_sub(1, (v))

#define atomic24_inc_return(v) __atomic24_add(1, (v))



#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)

#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)



#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))

#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))



#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)



/* Atomic operations are already serializing */

#define smp_mb__before_atomic_dec()	barrier()

#define smp_mb__after_atomic_dec()	barrier()

#define smp_mb__before_atomic_inc()	barrier()

#define smp_mb__after_atomic_inc()	barrier()



#endif /* !(__KERNEL__) */



#include <asm-generic/atomic.h>

#endif /* !(__ARCH_SPARC_ATOMIC__) */

include/asm-sparc/atomic_32.h

0 → 100644
+165 −0
Original line number Diff line number Diff line 
/* atomic.h: These still suck, but the I-cache hit rate is higher.

 *

 * Copyright (C) 1996 David S. Miller (davem@davemloft.net)

 * Copyright (C) 2000 Anton Blanchard (anton@linuxcare.com.au)

 * Copyright (C) 2007 Kyle McMartin (kyle@parisc-linux.org)

 *

 * Additions by Keith M Wesolowski (wesolows@foobazco.org) based

 * on asm-parisc/atomic.h Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>.

 */



#ifndef __ARCH_SPARC_ATOMIC__

#define __ARCH_SPARC_ATOMIC__



#include <linux/types.h>



typedef struct { volatile int counter; } atomic_t;



#ifdef __KERNEL__



#define ATOMIC_INIT(i)  { (i) }



extern int __atomic_add_return(int, atomic_t *);

extern int atomic_cmpxchg(atomic_t *, int, int);

#define atomic_xchg(v, new) (xchg(&((v)->counter), new))

extern int atomic_add_unless(atomic_t *, int, int);

extern void atomic_set(atomic_t *, int);



#define atomic_read(v)          ((v)->counter)



#define atomic_add(i, v)	((void)__atomic_add_return( (int)(i), (v)))

#define atomic_sub(i, v)	((void)__atomic_add_return(-(int)(i), (v)))

#define atomic_inc(v)		((void)__atomic_add_return(        1, (v)))

#define atomic_dec(v)		((void)__atomic_add_return(       -1, (v)))



#define atomic_add_return(i, v)	(__atomic_add_return( (int)(i), (v)))

#define atomic_sub_return(i, v)	(__atomic_add_return(-(int)(i), (v)))

#define atomic_inc_return(v)	(__atomic_add_return(        1, (v)))

#define atomic_dec_return(v)	(__atomic_add_return(       -1, (v)))



#define atomic_add_negative(a, v)	(atomic_add_return((a), (v)) < 0)



/*

 * atomic_inc_and_test - increment and test

 * @v: pointer of type atomic_t

 *

 * Atomically increments @v by 1

 * and returns true if the result is zero, or false for all

 * other cases.

 */

#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)



#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)

#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)



#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)



/* This is the old 24-bit implementation.  It's still used internally

 * by some sparc-specific code, notably the semaphore implementation.

 */

typedef struct { volatile int counter; } atomic24_t;



#ifndef CONFIG_SMP



#define ATOMIC24_INIT(i)  { (i) }

#define atomic24_read(v)          ((v)->counter)

#define atomic24_set(v, i)        (((v)->counter) = i)



#else

/* We do the bulk of the actual work out of line in two common

 * routines in assembler, see arch/sparc/lib/atomic.S for the

 * "fun" details.

 *

 * For SMP the trick is you embed the spin lock byte within

 * the word, use the low byte so signedness is easily retained

 * via a quick arithmetic shift.  It looks like this:

 *

 *	----------------------------------------

 *	| signed 24-bit counter value |  lock  |  atomic_t

 *	----------------------------------------

 *	 31                          8 7      0

 */



#define ATOMIC24_INIT(i)	{ ((i) << 8) }



static inline int atomic24_read(const atomic24_t *v)

{

	int ret = v->counter;



	while(ret & 0xff)

		ret = v->counter;



	return ret >> 8;

}



#define atomic24_set(v, i)	(((v)->counter) = ((i) << 8))

#endif



static inline int __atomic24_add(int i, atomic24_t *v)

{

	register volatile int *ptr asm("g1");

	register int increment asm("g2");

	register int tmp1 asm("g3");

	register int tmp2 asm("g4");

	register int tmp3 asm("g7");



	ptr = &v->counter;

	increment = i;



	__asm__ __volatile__(

	"mov	%%o7, %%g4\n\t"

	"call	___atomic24_add\n\t"

	" add	%%o7, 8, %%o7\n"

	: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)

	: "0" (increment), "r" (ptr)

	: "memory", "cc");



	return increment;

}



static inline int __atomic24_sub(int i, atomic24_t *v)

{

	register volatile int *ptr asm("g1");

	register int increment asm("g2");

	register int tmp1 asm("g3");

	register int tmp2 asm("g4");

	register int tmp3 asm("g7");



	ptr = &v->counter;

	increment = i;



	__asm__ __volatile__(

	"mov	%%o7, %%g4\n\t"

	"call	___atomic24_sub\n\t"

	" add	%%o7, 8, %%o7\n"

	: "=&r" (increment), "=r" (tmp1), "=r" (tmp2), "=r" (tmp3)

	: "0" (increment), "r" (ptr)

	: "memory", "cc");



	return increment;

}



#define atomic24_add(i, v) ((void)__atomic24_add((i), (v)))

#define atomic24_sub(i, v) ((void)__atomic24_sub((i), (v)))



#define atomic24_dec_return(v) __atomic24_sub(1, (v))

#define atomic24_inc_return(v) __atomic24_add(1, (v))



#define atomic24_sub_and_test(i, v) (__atomic24_sub((i), (v)) == 0)

#define atomic24_dec_and_test(v) (__atomic24_sub(1, (v)) == 0)



#define atomic24_inc(v) ((void)__atomic24_add(1, (v)))

#define atomic24_dec(v) ((void)__atomic24_sub(1, (v)))



#define atomic24_add_negative(i, v) (__atomic24_add((i), (v)) < 0)



/* Atomic operations are already serializing */

#define smp_mb__before_atomic_dec()	barrier()

#define smp_mb__after_atomic_dec()	barrier()

#define smp_mb__before_atomic_inc()	barrier()

#define smp_mb__after_atomic_inc()	barrier()



#endif /* !(__KERNEL__) */



#include <asm-generic/atomic.h>

#endif /* !(__ARCH_SPARC_ATOMIC__) */

include/asm-sparc/atomic_64.h

0 → 100644
+128 −0
Original line number Diff line number Diff line 
/* atomic.h: Thankfully the V9 is at least reasonable for this

 *           stuff.

 *

 * Copyright (C) 1996, 1997, 2000 David S. Miller (davem@redhat.com)

 */



#ifndef __ARCH_SPARC64_ATOMIC__

#define __ARCH_SPARC64_ATOMIC__



#include <linux/types.h>

#include <asm/system.h>



typedef struct { volatile int counter; } atomic_t;

typedef struct { volatile __s64 counter; } atomic64_t;



#define ATOMIC_INIT(i)		{ (i) }

#define ATOMIC64_INIT(i)	{ (i) }



#define atomic_read(v)		((v)->counter)

#define atomic64_read(v)	((v)->counter)



#define atomic_set(v, i)	(((v)->counter) = i)

#define atomic64_set(v, i)	(((v)->counter) = i)



extern void atomic_add(int, atomic_t *);

extern void atomic64_add(int, atomic64_t *);

extern void atomic_sub(int, atomic_t *);

extern void atomic64_sub(int, atomic64_t *);



extern int atomic_add_ret(int, atomic_t *);

extern int atomic64_add_ret(int, atomic64_t *);

extern int atomic_sub_ret(int, atomic_t *);

extern int atomic64_sub_ret(int, atomic64_t *);



#define atomic_dec_return(v) atomic_sub_ret(1, v)

#define atomic64_dec_return(v) atomic64_sub_ret(1, v)



#define atomic_inc_return(v) atomic_add_ret(1, v)

#define atomic64_inc_return(v) atomic64_add_ret(1, v)



#define atomic_sub_return(i, v) atomic_sub_ret(i, v)

#define atomic64_sub_return(i, v) atomic64_sub_ret(i, v)



#define atomic_add_return(i, v) atomic_add_ret(i, v)

#define atomic64_add_return(i, v) atomic64_add_ret(i, v)



/*

 * atomic_inc_and_test - increment and test

 * @v: pointer of type atomic_t

 *

 * Atomically increments @v by 1

 * and returns true if the result is zero, or false for all

 * other cases.

 */

#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)

#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)



#define atomic_sub_and_test(i, v) (atomic_sub_ret(i, v) == 0)

#define atomic64_sub_and_test(i, v) (atomic64_sub_ret(i, v) == 0)



#define atomic_dec_and_test(v) (atomic_sub_ret(1, v) == 0)

#define atomic64_dec_and_test(v) (atomic64_sub_ret(1, v) == 0)



#define atomic_inc(v) atomic_add(1, v)

#define atomic64_inc(v) atomic64_add(1, v)



#define atomic_dec(v) atomic_sub(1, v)

#define atomic64_dec(v) atomic64_sub(1, v)



#define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)

#define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0)



#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))

#define atomic_xchg(v, new) (xchg(&((v)->counter), new))



static inline int atomic_add_unless(atomic_t *v, int a, int u)

{

	int c, old;

	c = atomic_read(v);

	for (;;) {

		if (unlikely(c == (u)))

			break;

		old = atomic_cmpxchg((v), c, c + (a));

		if (likely(old == c))

			break;

		c = old;

	}

	return c != (u);

}



#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)



#define atomic64_cmpxchg(v, o, n) \

	((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))

#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))



static inline int atomic64_add_unless(atomic64_t *v, long a, long u)

{

	long c, old;

	c = atomic64_read(v);

	for (;;) {

		if (unlikely(c == (u)))

			break;

		old = atomic64_cmpxchg((v), c, c + (a));

		if (likely(old == c))

			break;

		c = old;

	}

	return c != (u);

}



#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)



/* Atomic operations are already serializing */

#ifdef CONFIG_SMP

#define smp_mb__before_atomic_dec()	membar_storeload_loadload();

#define smp_mb__after_atomic_dec()	membar_storeload_storestore();

#define smp_mb__before_atomic_inc()	membar_storeload_loadload();

#define smp_mb__after_atomic_inc()	membar_storeload_storestore();

#else

#define smp_mb__before_atomic_dec()	barrier()

#define smp_mb__after_atomic_dec()	barrier()

#define smp_mb__before_atomic_inc()	barrier()

#define smp_mb__after_atomic_inc()	barrier()

#endif



#include <asm-generic/atomic.h>

#endif /* !(__ARCH_SPARC64_ATOMIC__) */

include/asm-sparc/auxio.h

+8 −89
Original line number Diff line number Diff line 
/*

 * auxio.h:  Definitions and code for the Auxiliary I/O register.

 *

 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)

 */

#ifndef _SPARC_AUXIO_H

#define _SPARC_AUXIO_H



#include <asm/system.h>

#include <asm/vaddrs.h>



/* This register is an unsigned char in IO space.  It does two things.

 * First, it is used to control the front panel LED light on machines

 * that have it (good for testing entry points to trap handlers and irq's)

 * Secondly, it controls various floppy drive parameters.

 */

#define AUXIO_ORMEIN      0xf0    /* All writes must set these bits. */

#define AUXIO_ORMEIN4M    0xc0    /* sun4m - All writes must set these bits. */

#define AUXIO_FLPY_DENS   0x20    /* Floppy density, high if set. Read only. */

#define AUXIO_FLPY_DCHG   0x10    /* A disk change occurred.  Read only. */

#define AUXIO_EDGE_ON     0x10    /* sun4m - On means Jumper block is in. */

#define AUXIO_FLPY_DSEL   0x08    /* Drive select/start-motor. Write only. */

#define AUXIO_LINK_TEST   0x08    /* sun4m - On means TPE Carrier detect. */



/* Set the following to one, then zero, after doing a pseudo DMA transfer. */

#define AUXIO_FLPY_TCNT   0x04    /* Floppy terminal count. Write only. */



/* Set the following to zero to eject the floppy. */

#define AUXIO_FLPY_EJCT   0x02    /* Eject floppy disk.  Write only. */

#define AUXIO_LED         0x01    /* On if set, off if unset. Read/Write */



#ifndef __ASSEMBLY__



/* 

 * NOTE: these routines are implementation dependent-- 

 * understand the hardware you are querying! 

 */

extern void set_auxio(unsigned char bits_on, unsigned char bits_off);

extern unsigned char get_auxio(void); /* .../asm-sparc/floppy.h */



/*

 * The following routines are provided for driver-compatibility

 * with sparc64 (primarily sunlance.c)

 */



#define AUXIO_LTE_ON    1

#define AUXIO_LTE_OFF   0



/* auxio_set_lte - Set Link Test Enable (TPE Link Detect)

 *

 * on - AUXIO_LTE_ON or AUXIO_LTE_OFF

 */

#define auxio_set_lte(on) \

do { \

	if(on) { \

		set_auxio(AUXIO_LINK_TEST, 0); \

	} else { \

		set_auxio(0, AUXIO_LINK_TEST); \

	} \

} while (0)



#define AUXIO_LED_ON    1

#define AUXIO_LED_OFF   0



/* auxio_set_led - Set system front panel LED

 *

 * on - AUXIO_LED_ON or AUXIO_LED_OFF

 */

#define auxio_set_led(on) \

do { \

	if(on) { \

		set_auxio(AUXIO_LED, 0); \

	} else { \

		set_auxio(0, AUXIO_LED); \

	} \

} while (0)



#endif /* !(__ASSEMBLY__) */





/* AUXIO2 (Power Off Control) */

extern __volatile__ unsigned char * auxio_power_register;



#define	AUXIO_POWER_DETECT_FAILURE	32

#define	AUXIO_POWER_CLEAR_FAILURE	2

#define	AUXIO_POWER_OFF			1





#endif /* !(_SPARC_AUXIO_H) */
 
#ifndef ___ASM_SPARC_AUXIO_H

#define ___ASM_SPARC_AUXIO_H

#if defined(__sparc__) && defined(__arch64__)

#include <asm-sparc/auxio_64.h>

#else

#include <asm-sparc/auxio_32.h>

#endif

#endif