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Commit f556cb0c authored by Chunming Zhou's avatar Chunming Zhou Committed by Alex Deucher
Browse files

drm/amd: add scheduler fence implementation (v2)



scheduler fence is based on kernel fence framework.

v2: squash in Christian's build fix

Signed-off-by: default avatarChunming Zhou <david1.zhou@amd.com>
Reviewed-by: default avatarChristian K?nig <christian.koenig@amd.com>
parent 4af9f07c
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+1 −0
Original line number Diff line number Diff line
@@ -86,6 +86,7 @@ amdgpu-y += amdgpu_cgs.o
# GPU scheduler
amdgpu-y += \
	../scheduler/gpu_scheduler.o \
	../scheduler/sched_fence.o \
	amdgpu_sched.o

amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
+1 −0
Original line number Diff line number Diff line
@@ -1261,6 +1261,7 @@ struct amdgpu_cs_parser {
	int (*prepare_job)(struct amdgpu_cs_parser *sched_job);
	int (*run_job)(struct amdgpu_cs_parser *sched_job);
	int (*free_job)(struct amdgpu_cs_parser *sched_job);
	struct amd_sched_fence *s_fence;
};

static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p, uint32_t ib_idx, int idx)
+15 −6
Original line number Diff line number Diff line
@@ -899,8 +899,6 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
	if (amdgpu_enable_scheduler && parser->num_ibs) {
		struct amdgpu_ring * ring =
			amdgpu_cs_parser_get_ring(adev, parser);
		parser->ibs[parser->num_ibs - 1].sequence = atomic64_inc_return(
			&parser->ctx->rings[ring->idx].entity.last_queued_v_seq);
		if (ring->is_pte_ring || (parser->bo_list && parser->bo_list->has_userptr)) {
			r = amdgpu_cs_parser_prepare_job(parser);
			if (r)
@@ -910,10 +908,21 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
		parser->ring = ring;
		parser->run_job = amdgpu_cs_parser_run_job;
		parser->free_job = amdgpu_cs_parser_free_job;
		amd_sched_push_job(ring->scheduler,
		mutex_lock(&parser->job_lock);
		r = amd_sched_push_job(ring->scheduler,
				       &parser->ctx->rings[ring->idx].entity,
				   parser);
		cs->out.handle = parser->ibs[parser->num_ibs - 1].sequence;
				       parser,
				       &parser->s_fence);
		if (r) {
			mutex_unlock(&parser->job_lock);
			goto out;
		}
		parser->ibs[parser->num_ibs - 1].sequence =
			amdgpu_ctx_add_fence(parser->ctx, ring,
					     &parser->s_fence->base,
					     parser->s_fence->v_seq);
		cs->out.handle = parser->s_fence->v_seq;
		mutex_unlock(&parser->job_lock);
		up_read(&adev->exclusive_lock);
		return 0;
	}
+0 −10
Original line number Diff line number Diff line
@@ -268,16 +268,6 @@ struct fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
	struct amdgpu_ctx_ring *cring = & ctx->rings[ring->idx];
	struct fence *fence;
	uint64_t queued_seq;
	int r;

	if (amdgpu_enable_scheduler) {
		r = amd_sched_wait_emit(&cring->entity,
					seq,
					false,
					-1);
		if (r)
			return NULL;
	}

	spin_lock(&ctx->ring_lock);
	if (amdgpu_enable_scheduler)
+1 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,

	sequence = amdgpu_enable_scheduler ? ib->sequence : 0;

	if (ib->ctx)
	if (!amdgpu_enable_scheduler && ib->ctx)
		ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
						    &ib->fence->base,
						    sequence);
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