Loading drivers/clk/imx/clk-pllv3.c +8 −1 Original line number Original line Diff line number Diff line Loading @@ -24,12 +24,14 @@ #define BM_PLL_POWER (0x1 << 12) #define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) #define BM_PLL_LOCK (0x1 << 31) #define IMX7_ENET_PLL_POWER (0x1 << 5) /** /** * struct clk_pllv3 - IMX PLL clock version 3 * struct clk_pllv3 - IMX PLL clock version 3 * @clk_hw: clock source * @clk_hw: clock source * @base: base address of PLL registers * @base: base address of PLL registers * @powerup_set: set POWER bit to power up the PLL * @powerup_set: set POWER bit to power up the PLL * @powerdown: pll powerdown offset bit * @div_mask: mask of divider bits * @div_mask: mask of divider bits * @div_shift: shift of divider bits * @div_shift: shift of divider bits * * Loading @@ -40,6 +42,7 @@ struct clk_pllv3 { struct clk_hw hw; struct clk_hw hw; void __iomem *base; void __iomem *base; bool powerup_set; bool powerup_set; u32 powerdown; u32 div_mask; u32 div_mask; u32 div_shift; u32 div_shift; }; }; Loading @@ -49,7 +52,7 @@ struct clk_pllv3 { static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) { { unsigned long timeout = jiffies + msecs_to_jiffies(10); unsigned long timeout = jiffies + msecs_to_jiffies(10); u32 val = readl_relaxed(pll->base) & BM_PLL_POWER; u32 val = readl_relaxed(pll->base) & pll->powerdown; /* No need to wait for lock when pll is not powered up */ /* No need to wait for lock when pll is not powered up */ if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) Loading Loading @@ -293,6 +296,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, if (!pll) if (!pll) return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM); pll->powerdown = BM_PLL_POWER; switch (type) { switch (type) { case IMX_PLLV3_SYS: case IMX_PLLV3_SYS: ops = &clk_pllv3_sys_ops; ops = &clk_pllv3_sys_ops; Loading @@ -306,6 +311,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, case IMX_PLLV3_AV: case IMX_PLLV3_AV: ops = &clk_pllv3_av_ops; ops = &clk_pllv3_av_ops; break; break; case IMX_PLLV3_ENET_IMX7: pll->powerdown = IMX7_ENET_PLL_POWER; case IMX_PLLV3_ENET: case IMX_PLLV3_ENET: ops = &clk_pllv3_enet_ops; ops = &clk_pllv3_enet_ops; break; break; Loading drivers/clk/imx/clk.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -39,6 +39,7 @@ enum imx_pllv3_type { IMX_PLLV3_USB_VF610, IMX_PLLV3_USB_VF610, IMX_PLLV3_AV, IMX_PLLV3_AV, IMX_PLLV3_ENET, IMX_PLLV3_ENET, IMX_PLLV3_ENET_IMX7, }; }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, Loading Loading
drivers/clk/imx/clk-pllv3.c +8 −1 Original line number Original line Diff line number Diff line Loading @@ -24,12 +24,14 @@ #define BM_PLL_POWER (0x1 << 12) #define BM_PLL_POWER (0x1 << 12) #define BM_PLL_LOCK (0x1 << 31) #define BM_PLL_LOCK (0x1 << 31) #define IMX7_ENET_PLL_POWER (0x1 << 5) /** /** * struct clk_pllv3 - IMX PLL clock version 3 * struct clk_pllv3 - IMX PLL clock version 3 * @clk_hw: clock source * @clk_hw: clock source * @base: base address of PLL registers * @base: base address of PLL registers * @powerup_set: set POWER bit to power up the PLL * @powerup_set: set POWER bit to power up the PLL * @powerdown: pll powerdown offset bit * @div_mask: mask of divider bits * @div_mask: mask of divider bits * @div_shift: shift of divider bits * @div_shift: shift of divider bits * * Loading @@ -40,6 +42,7 @@ struct clk_pllv3 { struct clk_hw hw; struct clk_hw hw; void __iomem *base; void __iomem *base; bool powerup_set; bool powerup_set; u32 powerdown; u32 div_mask; u32 div_mask; u32 div_shift; u32 div_shift; }; }; Loading @@ -49,7 +52,7 @@ struct clk_pllv3 { static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) static int clk_pllv3_wait_lock(struct clk_pllv3 *pll) { { unsigned long timeout = jiffies + msecs_to_jiffies(10); unsigned long timeout = jiffies + msecs_to_jiffies(10); u32 val = readl_relaxed(pll->base) & BM_PLL_POWER; u32 val = readl_relaxed(pll->base) & pll->powerdown; /* No need to wait for lock when pll is not powered up */ /* No need to wait for lock when pll is not powered up */ if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) if ((pll->powerup_set && !val) || (!pll->powerup_set && val)) Loading Loading @@ -293,6 +296,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, if (!pll) if (!pll) return ERR_PTR(-ENOMEM); return ERR_PTR(-ENOMEM); pll->powerdown = BM_PLL_POWER; switch (type) { switch (type) { case IMX_PLLV3_SYS: case IMX_PLLV3_SYS: ops = &clk_pllv3_sys_ops; ops = &clk_pllv3_sys_ops; Loading @@ -306,6 +311,8 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, case IMX_PLLV3_AV: case IMX_PLLV3_AV: ops = &clk_pllv3_av_ops; ops = &clk_pllv3_av_ops; break; break; case IMX_PLLV3_ENET_IMX7: pll->powerdown = IMX7_ENET_PLL_POWER; case IMX_PLLV3_ENET: case IMX_PLLV3_ENET: ops = &clk_pllv3_enet_ops; ops = &clk_pllv3_enet_ops; break; break; Loading
drivers/clk/imx/clk.h +1 −0 Original line number Original line Diff line number Diff line Loading @@ -39,6 +39,7 @@ enum imx_pllv3_type { IMX_PLLV3_USB_VF610, IMX_PLLV3_USB_VF610, IMX_PLLV3_AV, IMX_PLLV3_AV, IMX_PLLV3_ENET, IMX_PLLV3_ENET, IMX_PLLV3_ENET_IMX7, }; }; struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, Loading