Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit f4f8e563 authored by Viresh Kumar's avatar Viresh Kumar Committed by Linus Walleij
Browse files

pinctrl: SPEAr: Add gpio ranges support 



Most of SPEAr SoCs, which support pinctrl, can configure & use pads as gpio.
This patch gpio enable support for SPEAr pinctrl drivers.

Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
Acked-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 50309a9c

drivers/pinctrl/spear/Kconfig

+4 −0
Original line number Diff line number Diff line
@@ -25,21 +25,25 @@ config PINCTRL_SPEAR310 
	bool "ST Microelectronics SPEAr310 SoC pin controller driver"

	depends on MACH_SPEAR310

	select PINCTRL_SPEAR3XX

	select PINCTRL_SPEAR_PLGPIO



config PINCTRL_SPEAR320

	bool "ST Microelectronics SPEAr320 SoC pin controller driver"

	depends on MACH_SPEAR320

	select PINCTRL_SPEAR3XX

	select PINCTRL_SPEAR_PLGPIO



config PINCTRL_SPEAR1310

	bool "ST Microelectronics SPEAr1310 SoC pin controller driver"

	depends on MACH_SPEAR1310

	select PINCTRL_SPEAR

	select PINCTRL_SPEAR_PLGPIO



config PINCTRL_SPEAR1340

	bool "ST Microelectronics SPEAr1340 SoC pin controller driver"

	depends on MACH_SPEAR1340

	select PINCTRL_SPEAR

	select PINCTRL_SPEAR_PLGPIO



config PINCTRL_SPEAR_PLGPIO

	bool "SPEAr SoC PLGPIO Controller"

drivers/pinctrl/spear/pinctrl-spear.c

+90 −17
Original line number Diff line number Diff line
@@ -18,6 +18,7 @@ 
#include <linux/module.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_gpio.h>

#include <linux/pinctrl/machine.h>

#include <linux/pinctrl/pinctrl.h>

#include <linux/pinctrl/pinmux.h>
@@ -38,6 +39,28 @@ static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) 
	writel_relaxed(val, pmx->vbase + reg);

}



static void muxregs_endisable(struct spear_pmx *pmx,

		struct spear_muxreg *muxregs, u8 count, bool enable)

{

	struct spear_muxreg *muxreg;

	u32 val, temp, j;



	for (j = 0; j < count; j++) {

		muxreg = &muxregs[j];



		val = pmx_readl(pmx, muxreg->reg);

		val &= ~muxreg->mask;



		if (enable)

			temp = muxreg->val;

		else

			temp = ~muxreg->val;



		val |= muxreg->mask & temp;

		pmx_writel(pmx, val, muxreg->reg);

	}

}



static int set_mode(struct spear_pmx *pmx, int mode)

{

	struct spear_pmx_mode *pmx_mode = NULL;
@@ -70,6 +93,17 @@ static int set_mode(struct spear_pmx *pmx, int mode) 
	return 0;

}



void __devinit

pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,

		unsigned count, u16 reg)

{

	int i = 0, j = 0;



	for (; i < count; i++)

		for (; j < gpio_pingroup[i].nmuxregs; j++)

			gpio_pingroup[i].muxregs[j].reg = reg;

}



void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)

{

	struct spear_pingroup *pgroup;
@@ -216,9 +250,7 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, 
	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);

	const struct spear_pingroup *pgroup;

	const struct spear_modemux *modemux;

	struct spear_muxreg *muxreg;

	u32 val, temp;

	int i, j;

	int i;

	bool found = false;



	pgroup = pmx->machdata->groups[group];
@@ -233,20 +265,8 @@ static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, 
		}



		found = true;

		for (j = 0; j < modemux->nmuxregs; j++) {

			muxreg = &modemux->muxregs[j];



			val = pmx_readl(pmx, muxreg->reg);

			val &= ~muxreg->mask;



			if (enable)

				temp = muxreg->val;

			else

				temp = ~muxreg->val;



			val |= muxreg->mask & temp;

			pmx_writel(pmx, val, muxreg->reg);

		}

		muxregs_endisable(pmx, modemux->muxregs, modemux->nmuxregs,

				enable);

	}



	if (!found) {
@@ -270,12 +290,65 @@ static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, 
	spear_pinctrl_endisable(pctldev, function, group, false);

}



/* gpio with pinmux */

static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,

		unsigned pin)

{

	struct spear_gpio_pingroup *gpio_pingroup;

	int i = 0, j;



	if (!pmx->machdata->gpio_pingroups)

		return NULL;



	for (; i < pmx->machdata->ngpio_pingroups; i++) {

		gpio_pingroup = &pmx->machdata->gpio_pingroups[i];



		for (j = 0; j < gpio_pingroup->npins; j++) {

			if (gpio_pingroup->pins[j] == pin)

				return gpio_pingroup;

		}

	}



	return ERR_PTR(-EINVAL);

}



static int gpio_request_endisable(struct pinctrl_dev *pctldev,

		struct pinctrl_gpio_range *range, unsigned offset, bool enable)

{

	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);

	struct spear_gpio_pingroup *gpio_pingroup;



	gpio_pingroup = get_gpio_pingroup(pmx, offset);

	if (IS_ERR(gpio_pingroup))

		return PTR_ERR(gpio_pingroup);



	if (gpio_pingroup)

		muxregs_endisable(pmx, gpio_pingroup->muxregs,

				gpio_pingroup->nmuxregs, enable);



	return 0;

}



static int gpio_request_enable(struct pinctrl_dev *pctldev,

		struct pinctrl_gpio_range *range, unsigned offset)

{

	return gpio_request_endisable(pctldev, range, offset, true);

}



static void gpio_disable_free(struct pinctrl_dev *pctldev,

		struct pinctrl_gpio_range *range, unsigned offset)

{

	gpio_request_endisable(pctldev, range, offset, false);

}



static struct pinmux_ops spear_pinmux_ops = {

	.get_functions_count = spear_pinctrl_get_funcs_count,

	.get_function_name = spear_pinctrl_get_func_name,

	.get_function_groups = spear_pinctrl_get_func_groups,

	.enable = spear_pinctrl_enable,

	.disable = spear_pinctrl_disable,

	.gpio_request_enable = gpio_request_enable,

	.gpio_disable_free = gpio_disable_free,

};



static struct pinctrl_desc spear_pinctrl_desc = {

drivers/pinctrl/spear/pinctrl-spear.h

+46 −0
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#ifndef __PINMUX_SPEAR_H__

#define __PINMUX_SPEAR_H__



#include <linux/gpio.h>

#include <linux/pinctrl/pinctrl.h>

#include <linux/types.h>
@@ -46,6 +47,44 @@ struct spear_muxreg { 
	u32 val;

};



struct spear_gpio_pingroup {

	const unsigned *pins;

	unsigned npins;

	struct spear_muxreg *muxregs;

	u8 nmuxregs;

};



/* ste: set to enable */

#define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste)		\

static struct spear_muxreg __pins##_muxregs[] = {		\

	{							\

		.reg = __muxreg,				\

		.mask = __mask,					\

		.val = __ste ? __mask : 0,			\

	},							\

}



#define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \

static struct spear_muxreg __pins##_muxregs[] = {		\

	{							\

		.reg = __muxreg1,				\

		.mask = __mask,					\

		.val = __ste1 ? __mask : 0,			\

	}, {							\

		.reg = __muxreg2,				\

		.mask = __mask,					\

		.val = __ste2 ? __mask : 0,			\

	},							\

}



#define GPIO_PINGROUP(__pins)					\

	{							\

		.pins = __pins,					\

		.npins = ARRAY_SIZE(__pins),			\

		.muxregs = __pins##_muxregs,			\

		.nmuxregs = ARRAY_SIZE(__pins##_muxregs),	\

	}



/**

 * struct spear_modemux - SPEAr mode mux configuration

 * @modes: mode ids supported by this group of muxregs
@@ -100,6 +139,8 @@ struct spear_function { 
 * @nfunctions: The numbmer of entries in @functions.

 * @groups: An array describing all pin groups the pin SoC supports.

 * @ngroups: The numbmer of entries in @groups.

 * @gpio_pingroups: gpio pingroups

 * @ngpio_pingroups: gpio pingroups count

 *

 * @modes_supported: Does SoC support modes

 * @mode: mode configured from probe
@@ -113,6 +154,8 @@ struct spear_pinctrl_machdata { 
	unsigned nfunctions;

	struct spear_pingroup **groups;

	unsigned ngroups;

	struct spear_gpio_pingroup *gpio_pingroups;

	unsigned ngpio_pingroups;



	bool modes_supported;

	u16 mode;
@@ -136,6 +179,9 @@ struct spear_pmx { 


/* exported routines */

void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);

void __devinit

pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,

		unsigned count, u16 reg);

int __devinit spear_pinctrl_probe(struct platform_device *pdev,

		struct spear_pinctrl_machdata *machdata);

int __devexit spear_pinctrl_remove(struct platform_device *pdev);

drivers/pinctrl/spear/pinctrl-spear1310.c

+264 −0
Original line number Diff line number Diff line
@@ -2418,6 +2418,268 @@ static struct spear_function *spear1310_functions[] = { 
	&gpt64_function,

};



static const unsigned pin18[] = { 18, };

static const unsigned pin19[] = { 19, };

static const unsigned pin20[] = { 20, };

static const unsigned pin21[] = { 21, };

static const unsigned pin22[] = { 22, };

static const unsigned pin23[] = { 23, };

static const unsigned pin54[] = { 54, };

static const unsigned pin55[] = { 55, };

static const unsigned pin56[] = { 56, };

static const unsigned pin57[] = { 57, };

static const unsigned pin58[] = { 58, };

static const unsigned pin59[] = { 59, };

static const unsigned pin60[] = { 60, };

static const unsigned pin61[] = { 61, };

static const unsigned pin62[] = { 62, };

static const unsigned pin63[] = { 63, };

static const unsigned pin143[] = { 143, };

static const unsigned pin144[] = { 144, };

static const unsigned pin145[] = { 145, };

static const unsigned pin146[] = { 146, };

static const unsigned pin147[] = { 147, };

static const unsigned pin148[] = { 148, };

static const unsigned pin149[] = { 149, };

static const unsigned pin150[] = { 150, };

static const unsigned pin151[] = { 151, };

static const unsigned pin152[] = { 152, };

static const unsigned pin205[] = { 205, };

static const unsigned pin206[] = { 206, };

static const unsigned pin211[] = { 211, };

static const unsigned pin212[] = { 212, };

static const unsigned pin213[] = { 213, };

static const unsigned pin214[] = { 214, };

static const unsigned pin215[] = { 215, };

static const unsigned pin216[] = { 216, };

static const unsigned pin217[] = { 217, };

static const unsigned pin218[] = { 218, };

static const unsigned pin219[] = { 219, };

static const unsigned pin220[] = { 220, };

static const unsigned pin221[] = { 221, };

static const unsigned pin222[] = { 222, };

static const unsigned pin223[] = { 223, };

static const unsigned pin224[] = { 224, };

static const unsigned pin225[] = { 225, };

static const unsigned pin226[] = { 226, };

static const unsigned pin227[] = { 227, };

static const unsigned pin228[] = { 228, };

static const unsigned pin229[] = { 229, };

static const unsigned pin230[] = { 230, };

static const unsigned pin231[] = { 231, };

static const unsigned pin232[] = { 232, };

static const unsigned pin233[] = { 233, };

static const unsigned pin234[] = { 234, };

static const unsigned pin235[] = { 235, };

static const unsigned pin236[] = { 236, };

static const unsigned pin237[] = { 237, };

static const unsigned pin238[] = { 238, };

static const unsigned pin239[] = { 239, };

static const unsigned pin240[] = { 240, };

static const unsigned pin241[] = { 241, };

static const unsigned pin242[] = { 242, };

static const unsigned pin243[] = { 243, };

static const unsigned pin244[] = { 244, };

static const unsigned pin245[] = { 245, };



static const unsigned pin_grp0[] = { 173, 174, };

static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };

static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,

	190, 191, 192, };

static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };

static const unsigned pin_grp4[] = { 199, 200, };

static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,

	75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };

static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };

static const unsigned pin_grp7[] = { 98, 99, };

static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,

	166, 167, 168, 169, 170, 171, 172, };



/* Define muxreg arrays */

DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);

DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);

DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);

DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);

DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);

DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);

DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);

DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);

DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);

DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);

DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);

DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);

DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);

DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);

DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);

DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);

DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);

DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);

DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);

DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);

DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);

DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);

DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);

DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);

DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);

DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);

DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);

DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);

DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);

DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);

DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);

DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);

DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);

DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);

DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);

DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);

DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);

DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);

DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);

DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);

DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);

DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);

DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);

DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);

DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);

DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);

DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);

DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);

DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);

DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);

DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);

DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);

DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);

DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);

DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);

DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);

DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);

DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);

DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);

DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);

DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);

DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);

DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);

DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);

DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);

DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);

DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);

DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);

DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);

DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);

DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);

DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);

DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);

DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);

DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);

DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);

DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);

DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);

DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);

DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);

DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);

DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);



static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {

	GPIO_PINGROUP(i2c0_pins),

	GPIO_PINGROUP(ssp0_pins),

	GPIO_PINGROUP(ssp0_cs0_pins),

	GPIO_PINGROUP(ssp0_cs1_2_pins),

	GPIO_PINGROUP(i2s0_pins),

	GPIO_PINGROUP(i2s1_pins),

	GPIO_PINGROUP(clcd_pins),

	GPIO_PINGROUP(clcd_high_res_pins),

	GPIO_PINGROUP(pin18),

	GPIO_PINGROUP(pin19),

	GPIO_PINGROUP(pin20),

	GPIO_PINGROUP(pin21),

	GPIO_PINGROUP(pin22),

	GPIO_PINGROUP(pin23),

	GPIO_PINGROUP(pin143),

	GPIO_PINGROUP(pin144),

	GPIO_PINGROUP(pin145),

	GPIO_PINGROUP(pin146),

	GPIO_PINGROUP(pin147),

	GPIO_PINGROUP(pin148),

	GPIO_PINGROUP(pin149),

	GPIO_PINGROUP(pin150),

	GPIO_PINGROUP(pin151),

	GPIO_PINGROUP(pin152),

	GPIO_PINGROUP(smi_2_chips_pins),

	GPIO_PINGROUP(pin54),

	GPIO_PINGROUP(pin55),

	GPIO_PINGROUP(pin56),

	GPIO_PINGROUP(pin57),

	GPIO_PINGROUP(pin58),

	GPIO_PINGROUP(pin59),

	GPIO_PINGROUP(pin60),

	GPIO_PINGROUP(pin61),

	GPIO_PINGROUP(pin62),

	GPIO_PINGROUP(pin63),

	GPIO_PINGROUP(pin_grp0),

	GPIO_PINGROUP(pin_grp1),

	GPIO_PINGROUP(pin_grp2),

	GPIO_PINGROUP(pin_grp3),

	GPIO_PINGROUP(pin_grp4),

	GPIO_PINGROUP(pin_grp5),

	GPIO_PINGROUP(pin_grp6),

	GPIO_PINGROUP(pin_grp7),

	GPIO_PINGROUP(pin_grp8),

	GPIO_PINGROUP(nand_16bit_pins),

	GPIO_PINGROUP(pin205),

	GPIO_PINGROUP(pin206),

	GPIO_PINGROUP(pin211),

	GPIO_PINGROUP(pin212),

	GPIO_PINGROUP(pin213),

	GPIO_PINGROUP(pin214),

	GPIO_PINGROUP(pin215),

	GPIO_PINGROUP(pin216),

	GPIO_PINGROUP(pin217),

	GPIO_PINGROUP(pin218),

	GPIO_PINGROUP(pin219),

	GPIO_PINGROUP(pin220),

	GPIO_PINGROUP(pin221),

	GPIO_PINGROUP(pin222),

	GPIO_PINGROUP(pin223),

	GPIO_PINGROUP(pin224),

	GPIO_PINGROUP(pin225),

	GPIO_PINGROUP(pin226),

	GPIO_PINGROUP(pin227),

	GPIO_PINGROUP(pin228),

	GPIO_PINGROUP(pin229),

	GPIO_PINGROUP(pin230),

	GPIO_PINGROUP(pin231),

	GPIO_PINGROUP(pin232),

	GPIO_PINGROUP(pin233),

	GPIO_PINGROUP(pin234),

	GPIO_PINGROUP(pin235),

	GPIO_PINGROUP(pin236),

	GPIO_PINGROUP(pin237),

	GPIO_PINGROUP(pin238),

	GPIO_PINGROUP(pin239),

	GPIO_PINGROUP(pin240),

	GPIO_PINGROUP(pin241),

	GPIO_PINGROUP(pin242),

	GPIO_PINGROUP(pin243),

	GPIO_PINGROUP(pin244),

	GPIO_PINGROUP(pin245),

	GPIO_PINGROUP(keyboard_rowcol6_8_pins),

	GPIO_PINGROUP(uart0_pins),

	GPIO_PINGROUP(uart0_modem_pins),

	GPIO_PINGROUP(gpt0_tmr0_pins),

	GPIO_PINGROUP(gpt0_tmr1_pins),

	GPIO_PINGROUP(gpt1_tmr0_pins),

	GPIO_PINGROUP(gpt1_tmr1_pins),

	GPIO_PINGROUP(touch_xy_pins),

};



static struct spear_pinctrl_machdata spear1310_machdata = {

	.pins = spear1310_pins,

	.npins = ARRAY_SIZE(spear1310_pins),
@@ -2425,6 +2687,8 @@ static struct spear_pinctrl_machdata spear1310_machdata = { 
	.ngroups = ARRAY_SIZE(spear1310_pingroups),

	.functions = spear1310_functions,

	.nfunctions = ARRAY_SIZE(spear1310_functions),

	.gpio_pingroups = spear1310_gpio_pingroup,

	.ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),

	.modes_supported = false,

};

drivers/pinctrl/spear/pinctrl-spear300.c

+2 −0
Original line number Diff line number Diff line
@@ -661,6 +661,8 @@ static int __devinit spear300_pinctrl_probe(struct platform_device *pdev) 
	spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups);

	spear3xx_machdata.functions = spear300_functions;

	spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions);

	spear3xx_machdata.gpio_pingroups = NULL;

	spear3xx_machdata.ngpio_pingroups = 0;



	spear3xx_machdata.modes_supported = true;

	spear3xx_machdata.pmx_modes = spear300_pmx_modes;