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Commit f47166d2 authored by Chris Wilson's avatar Chris Wilson Committed by Daniel Vetter
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drm/i915: Sanitize BIOS debugging bits from PIPECONF 

Quoting the BSpec from time immemorial:

  PIPEACONF, bits 28:27: Frame Start Delay (Debug)

  Used to delay the frame start signal that is sent to the display planes.
  Care must be taken to insure that there are enough lines during VBLANK
  to support this setting.

An instance of the BIOS leaving these bits set was found in the wild,
where it caused our modesetting to go all squiffy and skewiff.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47271


Reported-and-tested-by: default avatarEva Wang <evawang@linpus.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=43012


Reported-and-tested-by: default avatarCarl Richell <carl@system76.com>
Cc: stable@kernel.org
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent dd775ae2

drivers/gpu/drm/i915/i915_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -2385,6 +2385,7 @@ 
#define   PIPECONF_DISABLE	0

#define   PIPECONF_DOUBLE_WIDE	(1<<30)

#define   I965_PIPECONF_ACTIVE	(1<<30)

#define   PIPECONF_FRAME_START_DELAY_MASK (3<<27)

#define   PIPECONF_SINGLE_WIDE	0

#define   PIPECONF_PIPE_UNLOCKED 0

#define   PIPECONF_PIPE_LOCKED	(1<<25)

drivers/gpu/drm/i915/intel_display.c

+6 −0
Original line number Diff line number Diff line
@@ -7580,6 +7580,12 @@ static void intel_sanitize_modesetting(struct drm_device *dev, 
	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 reg, val;



	/* Clear any frame start delays used for debugging left by the BIOS */

	for_each_pipe(pipe) {

		reg = PIPECONF(pipe);

		I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);

	}



	if (HAS_PCH_SPLIT(dev))

		return;